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| User's Manual 78K0/KB1 8-Bit Single-Chip Microcontrollers PD780101 PD780102 PD780103 PD78F0103 PD780101(A) PD780102(A) PD780103(A) PD78F0103(A) PD780101(A1) PD780101(A2) PD780102(A1) PD780102(A2) PD780103(A1) PD780103(A2) PD78F0103(A1) Document No. U15836EJ4V0UD00 (4th edition) Date Published November 2003 N CP(K) c Printed in Japan [MEMO] 2 User's Manual U15836EJ4V0UD NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. TRON stands for The Realtime Operating system Nucleus. ITRON is an abbreviation of Industrial TRON. User's Manual U15836EJ4V0UD 3 These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited. * The information in this document is current as of June, 2003. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1 4 User's Manual U15836EJ4V0UD Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: * * * * * Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements * In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [GLOBAL SUPPORT] http://www.necel.com/en/support/support.html NEC Electronics America, Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 NEC Electronics (Europe) GmbH Duesseldorf, Germany Tel: 0211-65 03 01 * Sucursal en Espana Madrid, Spain Tel: 091-504 27 87 * Succursale Francaise Velizy-Villacoublay, France Tel: 01-30-67 58 00 * Filiale Italiana Milano, Italy Tel: 02-66 75 41 * Branch The Netherlands Eindhoven, The Netherlands Tel: 040-244 58 45 * Tyskland Filial Taeby, Sweden Tel: 08-63 80 820 * United Kingdom Branch Milton Keynes, UK Tel: 01908-691-133 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 NEC Electronics Hong Kong Ltd. Seoul Branch Seoul, Korea Tel: 02-558-3737 NEC Electronics Shanghai, Ltd. Shanghai, P.R. China Tel: 021-6841-1138 NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 NEC Electronics Singapore Pte. Ltd. Novena Square, Singapore Tel: 6253-8311 J03.4 User's Manual U15836EJ4V0UD 5 INTRODUCTION Readers This manual is intended for user engineers who wish to understand the functions of the 78K0/KB1 and design and develop application systems and programs for these devices. The target products are as follows. 78K0/KB1: PD780101, 780102, 780103, 78F0103, 780101(A), 780102(A), 780103(A), 78F0103(A), 780101(A1), 780102(A1), 780103(A1), 78F0103(A1), 780101(A2), 780102(A2), 780103(A2) Purpose This manual is intended to give users an understanding of the functions described in the Organization below. Organization The 78K0/KB1 manual is separated into two parts: this manual and the instructions edition (common to the 78K/0 Series). 78K0/KB1 User's Manual (This Manual) * Pin functions * Internal block functions * Interrupts * Other on-chip peripheral functions * Electrical specifications 78K/0 Series User's Manual Instructions * CPU functions * Instruction set * Explanation of each instruction 6 User's Manual U15836EJ4V0UD How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical engineering, logic circuits, and microcontrollers. * When using this manual as the manual for (A) grade, (A1) grade, and (A2) grade products: Only the quality grade differs between standard products and (A) grade, (A1) grade, and (A2) grade products. Read the part number as follows. * * * * PD780101 PD780101(A), 780101(A1), 780101(A2) PD780102 PD780102(A), 780102(A1), 780102(A2) PD780103 PD780103(A), 780103(A1), 780103(A2) PD78F0103 PD78F0103(A), 78F0103(A1) * To gain a general understanding of functions: Read this manual in the order of the CONTENTS. The mark revised points. * How to interpret the register format: For a bit number enclosed in brackets, the bit name is defined as a reserved word in the assembler, and is already defined in the header file named sfrbit.h in the C compiler. * To check the details of a register when you know the register name: Refer to APPENDIX C REGISTER INDEX. * To know details of the 78K/0 Series instructions: Refer to the separate document 78K/0 Series Instructions User's Manual (U12326E). Caution Examples in this manual employ the "standard" quality grade for general electronics. circuit actually used. Conventions Data significance: Note: Caution: Remark: Higher digits on the left and lower digits on the right Footnote for item marked with Note in the text Information requiring particular attention Supplementary information ... xxxx or xxxxB Decimal Hexadecimal ... xxxx ... xxxxH When using examples in this manual for the "special" quality grade, review the quality grade of each part and/or shows major Active low representations: xxx (overscore over pin and signal name) Numerical representations: Binary User's Manual U15836EJ4V0UD 7 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name 78K0/KB1 User's Manual 78K/0 Series Instructions User's Manual Document No. U15836E U12326E Documents Related to Development Tools (Software) (User's Manuals) Document Name RA78K0 Assembler Package Operation Language Structured Assembly Language CC78K0 C Compiler Operation Language SM78K Series System Simulator Ver. 2.30 or Later Operation (Windows TM Document No. U14445E U14446E U11789E U14297E U14298E Based) U15373E U15802E External Part User Open Interface Specifications ID78K Series Integrated Debugger Ver. 2.30 or Later RX78K0 Real-Time OS Operation (Windows Based) Fundamentals Installation Project Manager Ver. 3.12 or Later (Windows Based) U15185E U11537E U11536E U14610E Documents Related to Development Tools (Hardware) (User's Manuals) Document Name IE-78K0-NS In-Circuit Emulator IE-78K0-NS-A In-Circuit Emulator IE-78K0K1-ET In-Circuit Emulator IE-780148-NS-EM1 Emulation Board Document No. U13731E U14889E To be prepared To be prepared Documents Related to Flash Memory Programming Document Name PG-FP3 Flash Memory Programmer User's Manual PG-FP4 Flash Memory Programmer User's Manual Document No. U13502E U15260E Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document when designing. 8 User's Manual U15836EJ4V0UD Other Documents Document Name SEMICONDUCTOR SELECTION GUIDE - Products and Packages - Semiconductor Device Mount Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Document No. X13769X Note C11531E C10983E C11892E Note See the "Semiconductor Device Mount Manual" website (http://www.necel.com/pkg/en/mount/index.html). Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document when designing. User's Manual U15836EJ4V0UD 9 CONTENTS CHAPTER 1 OUTLINE ............................................................................................................................ 16 1.1 Features ...................................................................................................................................... 16 1.2 Applications................................................................................................................................ 17 1.3 Ordering Information ................................................................................................................. 18 1.4 Pin Configuration (Top View).................................................................................................... 20 1.5 K1 Family Lineup........................................................................................................................ 21 1.5.1 1.5.2 78K0/Kx1 product lineup................................................................................................................ 21 V850ES/Kx1 product lineup ........................................................................................................... 23 1.6 1.7 Block Diagram ............................................................................................................................ 25 Outline of Functions .................................................................................................................. 26 CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 28 2.1 Pin Function List ........................................................................................................................ 28 2.2 Description of Pin Functions .................................................................................................... 30 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 2.2.7 2.2.8 2.2.9 2.2.11 2.2.12 2.2.13 2.2.14 P00 to P03 (port 0) ........................................................................................................................ 30 P10 to P17 (port 1) ........................................................................................................................ 30 P20 to P23 (port 2) ........................................................................................................................ 31 P30 to P33 (port 3) ........................................................................................................................ 31 P120 (port 12)................................................................................................................................ 31 P130 (port 13)................................................................................................................................ 32 AVREF ............................................................................................................................................. 32 AVSS............................................................................................................................................... 32 RESET........................................................................................................................................... 32 VDD................................................................................................................................................. 32 VSS ................................................................................................................................................. 32 VPP (flash memory versions only) .................................................................................................. 32 IC (mask ROM versions only) ........................................................................................................ 32 2.2.10 X1 and X2 ...................................................................................................................................... 32 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins......................................... 33 CHAPTER 3 CPU ARCHITECTURE ...................................................................................................... 35 3.1 Memory Space ............................................................................................................................ 35 3.1.1 3.1.2 3.1.3 3.1.4 Internal program memory space .................................................................................................... 40 Internal data memory space .......................................................................................................... 41 Special function register (SFR) area.............................................................................................. 41 Data memory addressing............................................................................................................... 42 Control registers ............................................................................................................................ 46 General-purpose registers ............................................................................................................. 50 Special Function Registers (SFRs)................................................................................................ 51 Relative addressing ....................................................................................................................... 55 Immediate addressing ................................................................................................................... 56 Table indirect addressing............................................................................................................... 57 Register addressing....................................................................................................................... 57 User's Manual U15836EJ4V0UD 3.2 Processor Registers .................................................................................................................. 46 3.2.1 3.2.2 3.2.3 3.3 Instruction Address Addressing .............................................................................................. 55 3.3.1 3.3.2 3.3.3 3.3.4 10 3.4 Operand Address Addressing .................................................................................................. 58 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.4.7 3.4.8 3.4.9 Implied addressing .........................................................................................................................58 Register addressing........................................................................................................................59 Direct addressing............................................................................................................................60 Short direct addressing...................................................................................................................61 Special function register (SFR) addressing ....................................................................................62 Register indirect addressing ...........................................................................................................63 Based addressing...........................................................................................................................64 Based indexed addressing .............................................................................................................65 Stack addressing ............................................................................................................................66 CHAPTER 4 PORT FUNCTIONS........................................................................................................... 67 4.1 Port Functions............................................................................................................................ 67 4.2 Port Configuration ..................................................................................................................... 68 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 Port 0..............................................................................................................................................69 Port 1..............................................................................................................................................72 Port 2..............................................................................................................................................77 Port 3..............................................................................................................................................78 Port 12............................................................................................................................................79 Port 13............................................................................................................................................80 4.3 4.4 Registers Controlling Port Function ........................................................................................ 80 Port Function Operations.......................................................................................................... 84 4.4.1 4.4.2 4.4.3 Writing to I/O port ...........................................................................................................................84 Reading from I/O port .....................................................................................................................84 Operations on I/O port ....................................................................................................................84 CHAPTER 5 CLOCK GENERATOR ...................................................................................................... 85 5.1 Functions of Clock Generator .................................................................................................. 85 5.2 Configuration of Clock Generator ............................................................................................ 85 5.3 Registers Controlling Clock Generator ................................................................................... 87 5.4 System Clock Oscillator............................................................................................................ 93 5.4.1 5.4.2 5.4.3 X1 oscillator ....................................................................................................................................93 Ring-OSC oscillator ........................................................................................................................95 Prescaler ........................................................................................................................................95 5.5 5.6 5.7 5.8 Clock Generator Operation ....................................................................................................... 95 Time Required to Switch Between Ring-OSC Clock and X1 Input Clock .......................... 100 Time Required for CPU Clock Switchover ............................................................................ 100 Clock Switching Flowchart and Register Setting ................................................................. 101 5.8.1 5.8.2 5.8.3 Switching from Ring-OSC clock to X1 input clock ........................................................................101 Switching from X1 input clock to Ring-OSC clock ........................................................................102 Register settings...........................................................................................................................103 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00........................................................................... 104 6.1 Functions of 16-Bit Timer/Event Counter 00......................................................................... 104 6.2 Configuration of 16-Bit Timer/Event Counter 00 .................................................................. 105 6.3 Registers Controlling 16-Bit Timer/Event Counter 00.......................................................... 109 6.4 Operation of 16-Bit Timer/Event Counter 00 ......................................................................... 115 6.4.1 Interval timer operation.................................................................................................................115 User's Manual U15836EJ4V0UD 11 6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 PPG output operations .................................................................................................................118 Pulse width measurement operations ...........................................................................................121 External event counter operation ..................................................................................................129 Square-wave output operation......................................................................................................132 One-shot pulse output operation...................................................................................................134 6.5 Cautions for 16-Bit Timer/Event Counter 00 ......................................................................... 139 CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50 ............................................................................. 142 7.1 Functions of 8-Bit Timer/Event Counter 50 ........................................................................... 142 7.2 Configuration of 8-Bit Timer/Event Counter 50..................................................................... 143 7.3 Registers Controlling 8-Bit Timer/Event Counter 50 ............................................................ 145 7.4 Operations of 8-Bit Timer/Event Counter 50 ......................................................................... 148 7.4.1 7.4.2 7.4.3 7.4.4 Operation as interval timer............................................................................................................148 Operation as external event counter .............................................................................................150 Operation as square-wave output.................................................................................................151 Operation as PWM output.............................................................................................................152 7.5 Cautions for 8-Bit Timer/Event Counter 50............................................................................ 154 CHAPTER 8 8-BIT TIMERS H0 AND H1 .......................................................................................... 155 8.1 Functions of 8-Bit Timers H0 and H1 ..................................................................................... 155 8.2 Configuration of 8-Bit Timers H0 and H1............................................................................... 155 8.3 Registers Controlling 8-Bit Timers H0 and H1 ...................................................................... 159 8.4 Operation of 8-Bit Timers H0 and H1 ..................................................................................... 163 8.4.1 8.4.2 Operation as interval timer/square-wave output ...........................................................................163 Operation as PWM output mode...................................................................................................166 CHAPTER 9 WATCHDOG TIMER ....................................................................................................... 172 9.1 Functions of Watchdog Timer ................................................................................................ 172 9.2 Configuration of Watchdog Timer .......................................................................................... 174 9.3 Registers Controlling Watchdog Timer ................................................................................. 175 9.4 Operation of Watchdog Timer................................................................................................. 177 9.4.1 9.4.2 9.4.3 9.4.4 Watchdog timer operation when "Ring-OSC cannot be stopped" is selected by mask option ......177 Watchdog timer operation when "Ring-OSC can be stopped by software" is selected by mask option ............................................................................................................................................178 Watchdog timer operation in STOP mode (when "Ring-OSC can be stopped by software" is selected by mask option) ..............................................................................................................179 Watchdog timer operation in HALT mode (when "Ring-OSC can be stopped by software" is selected by mask option) ..............................................................................................................181 CHAPTER 10 A/D CONVERTER ......................................................................................................... 182 10.1 Function of A/D Converter ...................................................................................................... 182 10.2 Configuration of A/D Converter .............................................................................................. 183 10.3 Registers Used in A/D Converter............................................................................................ 185 10.4 A/D Converter Operations ....................................................................................................... 189 10.4.1 10.4.2 Basic operations of A/D converter ................................................................................................189 Input voltage and conversion results ............................................................................................191 10.4.3 A/D converter operation mode ......................................................................................................192 10.5 How to Read A/D Converter Characteristics Table............................................................... 195 12 User's Manual U15836EJ4V0UD 10.6 Cautions for A/D Converter..................................................................................................... 197 CHAPTER 11 SERIAL INTERFACE UART0 (PD780102, 780103, 78F0103 ONLY)...................... 202 11.1 Functions of Serial Interface UART0 ..................................................................................... 202 11.2 Configuration of Serial Interface UART0 ............................................................................... 203 11.3 Registers Controlling Serial Interface UART0 ...................................................................... 206 11.4 Operation of Serial Interface UART0...................................................................................... 211 11.4.1 Operation stop mode ....................................................................................................................211 11.4.2 11.4.3 Asynchronous serial interface (UART) mode................................................................................212 Dedicated baud rate generator .....................................................................................................218 CHAPTER 12 SERIAL INTERFACE UART6 ...................................................................................... 223 12.1 Functions of Serial Interface UART6 ..................................................................................... 223 12.2 Configuration of Serial Interface UART6 ............................................................................... 227 12.3 Registers Controlling Serial Interface UART6 ...................................................................... 230 12.4 Operation of Serial Interface UART6...................................................................................... 238 12.4.1 Operation stop mode ....................................................................................................................238 12.4.2 Asynchronous serial interface (UART) mode................................................................................239 12.4.3 Dedicated baud rate generator .....................................................................................................254 CHAPTER 13 SERIAL INTERFACE CSI10 ........................................................................................ 261 13.1 Functions of Serial Interface CSI10........................................................................................ 261 13.2 Configuration of Serial Interface CSI10 ................................................................................. 261 13.3 Registers Controlling Serial Interface CSI10 ........................................................................ 263 13.4 Operation of Serial Interface CSI10........................................................................................ 266 13.4.1 Operation stop mode ....................................................................................................................266 13.4.2 3-wire serial I/O mode ..................................................................................................................267 CHAPTER 14 INTERRUPT FUNCTIONS ............................................................................................ 275 14.1 Interrupt Function Types......................................................................................................... 275 14.2 Interrupt Sources and Configuration ..................................................................................... 275 14.3 Registers Controlling Interrupt Function .............................................................................. 278 14.4 Interrupt Servicing Operations ............................................................................................... 284 14.4.1 Maskable interrupt request acknowledgment ...............................................................................284 14.4.2 Software interrupt request acknowledgment.................................................................................286 14.4.3 14.4.4 Multiple interrupt servicing ............................................................................................................287 Interrupt request hold ...................................................................................................................290 CHAPTER 15 STANDBY FUNCTION.................................................................................................. 291 15.1 Standby Function and Configuration..................................................................................... 291 15.1.1 Standby function...........................................................................................................................291 15.1.2 Registers controlling standby function ..........................................................................................293 15.2 Standby Function Operation................................................................................................... 295 15.2.1 HALT mode ..................................................................................................................................295 15.2.2 STOP mode..................................................................................................................................298 CHAPTER 16 RESET FUNCTION ....................................................................................................... 302 16.1 Register for Confirming Reset Source .................................................................................. 308 User's Manual U15836EJ4V0UD 13 CHAPTER 17 CLOCK MONITOR ........................................................................................................ 309 17.1 Functions of Clock Monitor..................................................................................................... 309 17.2 Configuration of Clock Monitor .............................................................................................. 309 17.3 Register Controlling Clock Monitor........................................................................................ 310 17.4 Operation of Clock Monitor..................................................................................................... 311 CHAPTER 18 POWER-ON-CLEAR CIRCUIT...................................................................................... 316 18.1 Functions of Power-on-Clear Circuit...................................................................................... 316 18.2 Configuration of Power-on-Clear Circuit ............................................................................... 317 18.3 Operation of Power-on-Clear Circuit...................................................................................... 317 18.4 Cautions for Power-on-Clear Circuit ...................................................................................... 318 CHAPTER 19 LOW-VOLTAGE DETECTOR ....................................................................................... 320 19.1 Functions of Low-Voltage Detector........................................................................................ 320 19.2 Configuration of Low-Voltage Detector ................................................................................. 320 19.3 Registers Controlling Low-Voltage Detector ........................................................................ 321 19.4 Operation of Low-Voltage Detector........................................................................................ 323 19.5 Cautions for Low-Voltage Detector ........................................................................................ 327 CHAPTER 20 MASK OPTIONS ........................................................................................................... 330 CHAPTER 21 PD78F0103 .................................................................................................................... 331 21.1 Internal Memory Size Switching Register.............................................................................. 332 21.2 Writing with Flash Programmer.............................................................................................. 333 21.3 Programming Environment..................................................................................................... 340 21.4 Communication Mode.............................................................................................................. 340 21.5 Handling of Pins on Board ...................................................................................................... 344 21.5.1 21.5.2 21.5.3 21.5.4 21.5.5 VPP pin ..........................................................................................................................................344 Serial interface pins ......................................................................................................................344 RESET pin ....................................................................................................................................346 Port pins........................................................................................................................................346 Other signal pins...........................................................................................................................346 21.5.6 Power supply ................................................................................................................................346 21.6 Programming Method .............................................................................................................. 347 21.6.1 Controlling flash memory ..............................................................................................................347 21.6.2 Flash memory programming mode ...............................................................................................347 21.6.3 Selecting communication mode ....................................................................................................348 21.6.4 Communication commands ..........................................................................................................349 CHAPTER 22 INSTRUCTION SET....................................................................................................... 350 22.1 Conventions Used in Operation List ...................................................................................... 350 22.1.1 Operand identifiers and specification methods .............................................................................350 22.1.2 Description of operation column ...................................................................................................351 22.1.3 Description of flag operation column.............................................................................................351 22.2 Operation List ........................................................................................................................... 352 22.3 Instructions Listed by Addressing Type................................................................................ 360 14 User's Manual U15836EJ4V0UD CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) .................................................................................................................. 363 CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)................................ 380 CHAPTER 25 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS)................................ 395 CHAPTER 26 PACKAGE DRAWING .................................................................................................. 405 CHAPTER 27 RECOMMENDED SOLDERING CONDITIONS............................................................ 406 CHAPTER 28 CAUTIONS FOR WAIT ................................................................................................ 408 28.1 Cautions for Wait ..................................................................................................................... 408 28.2 Peripheral Hardware That Generates Wait ............................................................................ 409 28.3 Example of Wait Occurrence .................................................................................................. 410 APPENDIX A DEVELOPMENT TOOLS .............................................................................................. 411 A.1 Software Package .................................................................................................................... 414 A.2 Language Processing Software ............................................................................................. 415 A.3 Control Software ...................................................................................................................... 416 A.4 Flash Memory Writing Tools................................................................................................... 416 A.5 Debugging Tools (Hardware).................................................................................................. 417 A.5.1 A.5.2 When using in-circuit emulators IE-78K0-NS and IE-78K0-NS-A .................................................417 When using in-circuit emulator IE-78K0K1-ET .............................................................................418 A.6 Debugging Tools (Software) ................................................................................................... 419 A.7 Embedded Software ................................................................................................................ 420 APPENDIX B NOTES ON TARGET SYSTEM DESIGN................................................................... 421 APPENDIX C REGISTER INDEX......................................................................................................... 423 C.1 Register Index (In Alphabetical Order with Respect to Register Names) .......................... 423 C.2 Register Index (In Alphabetical Order with Respect to Register Symbol) ......................... 426 APPENDIX D REVISION HISTORY ..................................................................................................... 429 D.1 Major Revisions in This Edition.............................................................................................. 429 D.2 Revision History of Previous Editions................................................................................... 433 User's Manual U15836EJ4V0UD 15 CHAPTER 1 OUTLINE 1.1 Features Minimum instruction execution time can be changed from high speed (0.2 s: @ 10 MHz operation with X1 input clock) to low-speed (3.2 s: @ 10 MHz operation with X1 input clock) General-purpose register: 8 bits x 32 registers (8 bits x 8 registers x 4 banks) ROM, RAM capacities Part Number Item Program Memory (ROM) Mask ROM 8 KB 16 KB 24 KB Flash memory 24 KB Note Data Memory (Internal High-Speed RAM) 512 bytes 768 bytes PD780101 PD780102 PD780103 PD78F0103 Note The internal flash memory and internal high-speed RAM capacities can be changed using the internal memory size switching register (IMS). On-chip power-on-clear (POC) circuit and low-voltage detector (LVI) Short startup is possible via the CPU default start using the on-chip Ring-OSC On-chip clock monitor function using on-chip Ring-OSC On-chip watchdog timer (operable with Ring-OSC clock) I/O ports: 22 Timer: 5 channels Serial interface: CSI1/UARTNote: 10-bit resolution Supply voltage: 2 channels 1 channel (PD780101 only, CSI1: 1 channel) A/D converter: 4 channels VDD = 2.7 to 5.5 V (standard products, (A) grade products) VDD = 3.3 to 5.5 V ((A1) grade, (A2) grade products) Operating ambient temperature: TA = -40 to +85C (standard product, (A) grade product) TA = -40 to +105C (flash memory version of (A1) grade product) TA = -40 to +110C (mask ROM version of (A1) grade product) TA = -40 to +125C (mask ROM version of (A2) grade product) Note Select either of the functions of these alternate-function pins. UART (LIN (Local Interconnect Network)-bus supported): 1 channel 16 User's Manual U15836EJ4V0UD CHAPTER 1 OUTLINE 1.2 Applications Automotive equipment * System control for body electricals (power windows, keyless entry reception, etc.) * Sub-microcontrollers for control Home audio, car audio AV equipment PC peripheral equipment (keyboards, etc.) Household electrical appliances * Outdoor air conditioner units * Microwave ovens, electric rice cookers Industrial equipment * Pumps * Vending machines * FA (Factory Automation) User's Manual U15836EJ4V0UD 17 CHAPTER 1 OUTLINE 1.3 Ordering Information (1) Mask ROM version Part Number Package 30-pin plastic SSOP (7.62 mm (300)) 30-pin plastic SSOP (7.62 mm (300)) 30-pin plastic SSOP (7.62 mm (300)) 30-pin plastic SSOP (7.62 mm (300)) 30-pin plastic SSOP (7.62 mm (300)) 30-pin plastic SSOP (7.62 mm (300)) 30-pin plastic SSOP (7.62 mm (300)) 30-pin plastic SSOP (7.62 mm (300)) 30-pin plastic SSOP (7.62 mm (300)) 30-pin plastic SSOP (7.62 mm (300)) 30-pin plastic SSOP (7.62 mm (300)) 30-pin plastic SSOP (7.62 mm (300)) Quality Grade Standard Standard Standard Special Special Special Special Special Special Special Special Special PD780101MC-xxx-5A4 PD780102MC-xxx-5A4 PD780103MC-xxx-5A4 PD780101MC(A)-xxx-5A4 PD780102MC(A)-xxx-5A4 PD780103MC(A)-xxx-5A4 PD780101MC(A1)-xxx-5A4 PD780102MC(A1)-xxx-5A4 PD780103MC(A1)-xxx-5A4 PD780101MC(A2)-xxx-5A4 PD780102MC(A2)-xxx-5A4 PD780103MC(A2)-xxx-5A4 (2) Flash memory version Part Number Package 30-pin plastic SSOP (7.62 mm (300)) 30-pin plastic SSOP (7.62 mm (300)) 30-pin plastic SSOP (7.62 mm (300)) 30-pin plastic SSOP (7.62 mm (300)) 30-pin plastic SSOP (7.62 mm (300)) 30-pin plastic SSOP (7.62 mm (300)) 30-pin plastic SSOP (7.62 mm (300)) 30-pin plastic SSOP (7.62 mm (300)) 30-pin plastic SSOP (7.62 mm (300)) 30-pin plastic SSOP (7.62 mm (300)) 30-pin plastic SSOP (7.62 mm (300)) 30-pin plastic SSOP (7.62 mm (300)) 30-pin plastic SSOP (7.62 mm (300)) 30-pin plastic SSOP (7.62 mm (300)) 30-pin plastic SSOP (7.62 mm (300)) 30-pin plastic SSOP (7.62 mm (300)) Quality Grade Standard Standard Standard Standard Standard Standard Special Special Special Special Special Special Special Special Special Special PD78F0103M1MC-5A4 PD78F0103M2MC-5A4 PD78F0103M3MC-5A4 PD78F0103M4MC-5A4 PD78F0103M5MC-5A4 PD78F0103M6MC-5A4 PD78F0103M1MC(A)-5A4 PD78F0103M2MC(A)-5A4 PD78F0103M3MC(A)-5A4 PD78F0103M4MC(A)-5A4 PD78F0103M5MC(A)-5A4 PD78F0103M6MC(A)-5A4 PD78F0103M1MC(A1)-5A4 PD78F0103M2MC(A1)-5A4 PD78F0103M5MC(A1)-5A4 PD78F0103M6MC(A1)-5A4 Remark xxx indicates ROM code suffix. Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Electronics Corporation to know the specification of quality grade on the devices and its recommended applications. 18 User's Manual U15836EJ4V0UD CHAPTER 1 OUTLINE Mask ROM versions (PD780101, 780102, and 780103) include mask options. When ordering, it is possible to select "Power-on-clear (POC) circuit can be used/cannot be used" and "Ring-OSC clock can be stopped/cannot be stopped by software". Flash memory versions supporting the mask options of the mask ROM versions are as follows. Table 1-1. Flash Memory Versions Supporting Mask Options of Mask ROM Versions Mask Option POC Circuit POC cannot be used Ring-OSC Cannot be stopped Flash Memory Versions (Part Number) PD78F0103M1MC-5A4 PD78F0103M1MC(A)-5A4 PD78F0103M1MC(A1)-5A4 PD78F0103M2MC-5A4 PD78F0103M2MC(A)-5A4 PD78F0103M2MC(A1)-5A4 PD78F0103M3MC-5A4 PD78F0103M3MC(A)-5A4 PD78F0103M4MC-5A4 PD78F0103M4MC(A)-5A4 PD78F0103M5MC-5A4 PD78F0103M5MC(A)-5A4 PD78F0103M5MC(A1)-5A4 PD78F0103M6MC-5A4 PD78F0103M6MC(A)-5A4 PD78F0103M6MC(A1)-5A4 Can be stopped by software POC used (VPOC = 2.85 V 0.15 V) Cannot be stopped Can be stopped by software POC used (VPOC = 3.5 V 0.2 V) Cannot be stopped Can be stopped by software User's Manual U15836EJ4V0UD 19 CHAPTER 1 OUTLINE 1.4 Pin Configuration (Top View) * 30-pin plastic SSOP (7.62 mm (300)) P33/INTP4 P32/INTP3 P31/INTP2 P30/INTP1 IC (VPP) VSS VDD X1 X2 RESET P03 P02 P01/TI010/TO00 P00/TI000 P10/SCK10/TxD0Note 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P120/INTP0 AVSS AVREF P20/ANI0 P21/ANI1 P22/ANI2 P23/ANI3 P130 P17/TI50/TO50 P16/TOH1/INTP5 P15/TOH0 P14/RxD6 P13/TxD6 P12/SO10 P11/SI10/RxD0Note Note TxD0 and RxD0 are available only in the PD780102, 780103, and 78F0103. Cautions 1. Connect the IC (Internally Connected) pin directly to VSS. 2. Connect the AVSS pin to VSS. 3. Connect the VPP pin to VSS during normal operation. Remark Figures in parentheses apply only to the PD78F0103. Pin Identification ANI0 to ANI3: AVREF: IC: P00 to P03: P10 to P17: P20 to P23: P30 to P33: P120: P130: RESET: Analog input Analog reference voltage Internally connected Port 0 Port 1 Port 2 Port 3 Port 12 Port 13 Reset RxD0Note, RxD6: SCK10: SI10: SO10: TI000, TI010, TI50: TxD0Note, TxD6: VDD: VPP: VSS: X1, X2: Receive data Serial clock input/output Serial data input Serial data output Timer input Transmit data Power supply Programming power supply Ground Crystal oscillator (X1 input clock) INTP0 to INTP5: External interrupt input TO00, TO50, TOH0, TOH1: Timer output Note TxD0 and RxD0 are available only in the PD780102, 780103, and 78F0103. 20 User's Manual U15836EJ4V0UD CHAPTER 1 OUTLINE 1.5 K1 Family Lineup 1.5.1 78K0/Kx1 product lineup 78K0/KB1: 30-pin SSOP (7.62 mm 0.65 mm pitch) PD78F0103 PD780103 PD780102 PD780101 Flash memory: 24 KB, RAM: 768 bytes Mask ROM: 24 KB, RAM: 768 bytes Mask ROM: 16 KB, RAM: 768 bytes Mask ROM: 8 KB, RAM: 512 bytes 78K0/KC1: 44-pin LQFP (10 x 10 mm 0.8 mm pitch) PD78F0114 PD780114 PD780113 PD780112 PD780111 Flash memory: 32 KB, RAM: 1 KB Mask ROM: 32 KB, RAM: 1 KB Mask ROM: 24 KB, RAM: 1 KB Mask ROM: 16 KB, RAM: 512 bytes Mask ROM: 8 KB, RAM: 512 bytes 78K0/KD1: 52-pin LQFP (10 x 10 mm 0.65 mm pitch) PD78F0124 PD780124 PD780123 PD780122 PD780121 Flash memory: 32 KB, RAM: 1 KB Mask ROM: 32 KB, RAM: 1 KB Mask ROM: 24 KB, RAM: 1 KB Mask ROM: 16 KB, RAM: 512 bytes Mask ROM: 8 KB, RAM: 512 bytes 78K0/KE1: 64-pin LQFP, TQFP (10 x 10 mm 0.5 mm pitch, 12 x 12 mm 0.65 mm pitch, 14 x 14 mm 0.8 mm pitch) PD78F0134 PD780134 PD780133 PD780132 PD780131 Flash memory: 32 KB, RAM: 1 KB Mask ROM: 32 KB, RAM: 1 KB Mask ROM: 24 KB, RAM: 1 KB Mask ROM: 16 KB, RAM: 512 bytes Mask ROM: 8 KB, RAM: 512 bytes PD78F0138 PD780138 Flash memory: 60 KB, RAM: 2 KB Mask ROM: 60 KB, RAM: 2 KB Mask ROM: 48 KB, RAM: 2 KB PD780136 78K0/KF1: 80-pin TQFP, QFP (12 x 12 mm 0.5 mm pitch, 14 x 14 mm 0.65 mm pitch) PD78F0148 PD780148 PD780146 PD780144 PD780143 Flash memory: 60 KB, RAM: 2 KB Mask ROM: 60 KB, RAM: 2 KB Mask ROM: 48 KB, RAM: 2 KB Mask ROM: 32 KB, RAM: 1 KB Mask ROM: 24 KB, RAM: 1 KB User's Manual U15836EJ4V0UD 21 CHAPTER 1 OUTLINE The list of functions in the 78K0/Kx1 is shown below. Part Number Item Package Internal memory (bytes) Mask ROM 30 pins 8 K 16 K 24 K Flash memory RAM Power supply voltage Minimum instruction execution time 0.2 s (when 10 MHz, VDD = 4.0 to 5.5 V) 0.24 s (when 8.38 MHz, VDD = 3.3 to 5.5 V) 0.4 s (when 5 MHz, VDD = 2.7 to 5.5 V) - 17 4 1 - 1 ch 1 ch 2 ch - 1 ch Note 78K0/KB1 78K0/KC1 78K0/KD1 78K0/KE1 78K0/KF1 44 pins - 8 K 24 K 16 K 32 K - 512 - 32 K 1K 52 pins 8 K 24 K 16 K 32 K - 512 32 K 1K 512 - 64 pins 8 K 24 K 16 K 32 K - 32 K 1K - 48 K 60 K - 60 K 2K 1K - 80 pins 24 K 48 K 32 K 60 K - 60 K 2K - - 512 24 K 768 VDD = 2.7 to 5.5 V Clock X1 input Sub Ring-OSC 2 to 10 MHz 32.768 kHz 240 kHz (TYP.) 19 26 8 38 54 Port CMOS I/O CMOS input CMOS output N-ch open-drain I/O 4 2 ch 2 ch 1 ch 2 ch Timer 16 bits (TM0) 8 bits (TM5) 8 bits (TMH) For watch WDT 1 ch Serial 3-wire CSI interface Automatic transmit/ receive 3-wire CSI UART Note 1 ch - - 4 ch 6 11 - 12 4 ch Provided 7 15 8 16 1 ch 1 ch 8 ch 9 2 ch 1 ch 2 ch 1 ch UART supporting LIN-bus 10-bit A/D converter Interrupt External Internal Key return input Reset RESET pin POC LVI Clock monitor WDT Multiplier/divider ROM correction Standby function Operating ambient temperature - - 9 19 17 20 8 ch 2.85 V 0.15 V/3.5 V 0.20 V (selectable by mask option) 3.1 V/3.3 V 0.15 V/3.5 V/3.7 V/3.9 V/4.1 V/4.3 V 0.2 V (selectable by software) Provided Provided 16 bits x 16 bits, 32 bits / 16 bits Provided HALT/STOP mode Standard products, special (A) products: -40 to +85C Special (A1) products: -40 to +110C (mask ROM version), -40 to +105C (flash memory version) Special (A2) products: -40 to +125C (mask ROM version) - Note Select either of the functions of these alternate-function pins. 22 User's Manual U15836EJ4V0UD CHAPTER 1 OUTLINE 1.5.2 V850ES/Kx1 product lineup V850ES/KF1 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) PD703208 PD703208Y PD703209 PD703209Y PD703210 PD703210Y PD70F3210 PD70F3210Y Mask ROM: 64 KB, RAM: 4 KB I2C products Mask ROM: 96 KB, RAM: 4 KB I2C products Mask ROM: 128 KB, RAM: 6 KB I2C products Flash memory: 128 KB, RAM: 6 KB I2C products V850ES/KG1 100-pin plastic LQFP (fine pitch) (14 x 14) PD703212 PD703212Y PD703213 PD703213Y PD703214 PD703214Y PD70F3214 PD70F3214Y Mask ROM: 64 KB, RAM: 4 KB I2C products Mask ROM: 96 KB, RAM: 4 KB I2C products Mask ROM: 128 KB, RAM: 6 KB I2C products Flash memory: 128 KB, RAM: 6 KB I2C products V850ES/KJ1 144-pin plastic LQFP (fine pitch) (20 x 20) PD703216 PD703216Y PD703217 PD703217Y PD70F3217 PD70F3217Y Mask ROM: 96 KB, RAM: 6 KB I2C products Mask ROM: 128 KB, RAM: 6 KB I2C products Flash memory: 128 KB, RAM: 6 KB I2C products User's Manual U15836EJ4V0UD 23 CHAPTER 1 OUTLINE The list of functions in the V850ES/Kx1 is shown below. Function Part No. Timer 8-Bit 16-Bit TMH Watch WDT 2 ch 2 ch 2 ch 1 ch 2 ch CSI 2 ch Serial Interface CSIA 1 ch UART 2 ch IC - 1 ch - 1 ch - 1 ch - 1 ch 2 ch 4 ch 2 ch 1 ch 2 ch 2 ch 2 ch 2 ch - 1 ch - 1 ch - 1 ch - 1 ch 2 ch 6 ch 2 ch 1 ch 2 ch 3 ch 2 ch 3 ch - 2 ch - 2 ch - 2 ch 16 ch 2 ch 12 ch 128 - 8 ch 2 ch 6 ch 84 - 8 ch - 6 ch 67 - 2 A/D D/A RTO I/O Other PD703208 PD703208Y V850ES/KF1 V850ES/KG1 V850ES/KJ1 PD703209 PD703209Y PD703210 PD703210Y PD70F3210 PD70F3210Y PD703212 PD703212Y PD703213 PD703213Y PD703214 PD703214Y PD70F3214 PD70F3214Y PD703216 PD703216Y PD703217 PD703217Y PD70F3217 PD70F3217Y 24 User's Manual U15836EJ4V0UD CHAPTER 1 OUTLINE 1.6 Block Diagram TO00/TI010/P01 TI000/P00 16-bit timer/ event counter 00 Port 0 4 P00 to P03 Port 1 TOH0/P15 8-bit timer H0 Port 2 8 P10 to P17 4 P20 to P23 TOH1/P16 8-bit timer H1 Port 3 4 P30 to P33 TI50/TO50/P17 8-bit timer/ event counter 50 78K/0 CPU core ROM (Flash memory) Port 12 P120 Port 13 P130 Watchdog timer Clock monitor RxD0Note/P11 TxD0Note/P10 Serial interface UART0Note Internal high-speed RAM Power-on-clear/ low voltage indicator Reset control POC/LVI control RxD6/P14 TxD6/P13 SI1/P11 SO10/P12 SCK10/P10 ANI0/P20 to ANI3/P23 AVREF AVSS INTP0/P120 INTP1/P30 to INTP4/P33 4 Serial interface UART6 Serial interface CSI10 Ring-OSC A/D converter System control RESET X1 X2 Interrupt control 4 VDD VSS IC (VPP) Note PD780102, 780103, and 78F0103 only. Remark Items in parentheses are available only in the PD78F0103. User's Manual U15836EJ4V0UD 25 CHAPTER 1 OUTLINE 1.7 Outline of Functions Item Internal memory ROM High-speed RAM Memory space X1 input clock (oscillation frequency) Standard products, (A) grade products PD780101 8 KB 512 bytes 64 KB PD780102 16 KB 768 bytes PD780103 24 KB PD78F0103 24 KB (flash memory) Ceramic/crystal/external clock oscillation 10 MHz (VDD = 4.0 to 5.5 V), 8.38 MHz (VDD = 3.3 to 5.5 V), 5 MHz (VDD = 2.7 to 5.5 V) (A1) grade products 10 MHz (VDD = 4.5 to 5.5 V), 8.38 MHz (VDD = 4.0 to 5.5 V), 5 MHz (VDD = 3.3 to 5.5 V) (A2) grade products 8.38 MHz (VDD = 4.0 to 5.5 V), 5 MHz (VDD = 3.3 to 5.5 V) Ring-OSC clock (oscillation frequency) General-purpose registers Minimum instruction execution time On-chip Ring oscillation (240 kHz (TYP.)) 8 bits x 32 registers (8 bits x 8 registers x 4 banks) 0.2 s/0.4 s/0.8 s/1.6 s/3.2 s (X1 input clock: @ fXP = 10 MHz operation) 8.3 s/16.6 s/33.2 s/66.4 s/132.8 s (TYP.) (Ring-OSC clock: @ fR = 240 kHz (TYP.) operation) Instruction set * * * * 16-bit operation Multiply/divide (8 bits x 8 bits, 16 bits / 8 bits) Bit manipulate (set, reset, test, and Boolean operation) BCD adjust, etc. 22 17 4 1 1 channel 1 channel 2 channels 1 channel I/O ports Total: CMOS I/O CMOS input CMOS output Timers * * * * Timer outputs 16-bit timer/event counter: 8-bit timer/event counter: 8-bit timer: Watchdog timer: 4 (PWM: 3) 10-bit resolution x 4 channels * UART mode supporting LIN-bus: 1 channel Note * 3-wire serial I/O mode/UART mode : 1 channel (PD780101 only, 3-wire serial I/O mode: 1 channel) A/D converter Serial interface Vectored interrupt sources Reset Internal External 10 6 * * * * * 12 Reset using RESET pin Internal reset by watchdog timer Internal reset by clock monitor Internal reset by power-on-clear Internal reset by low-voltage detector Supply voltage Operating ambient temperature * Standard products, (A) grade products: VDD = 2.7 to 5.5 V * (A1) grade products, (A2) grade products: VDD = 3.3 to 5.5 V * Standard products, (A) grade products: TA = -40 to +85C * (A1) grade products: TA = -40 to +110C (mask ROM version), -40 to +105C (flash memory version) * (A2) grade products: TA = -40 to +125C (mask ROM versions) 30-pin plastic SSOP (7.62 mm (300)) Package Note Select either of the functions of these alternate-function pins. 26 User's Manual U15836EJ4V0UD CHAPTER 1 OUTLINE An outline of the timer is shown below. 16-Bit Timer/Event Counter 00 Operation mode Function Interval timer External event counter Timer output PPG output PWM output Pulse width measurement Square-wave output Interrupt source 1 channel 1 channel 1 output 1 output - 2 inputs 1 output 2 8-Bit Timer/Event Counter 50 1 channel 1 channel 1 output - 1 output - 1 output 1 8-Bit Timers H0 and H1 TMH0 1 channel - 1 output - 1 output - 1 output 1 TMH1 1 channel - 1 output - 1 output - 1 output 1 1 channel - - - - - - - Watchdog Timer User's Manual U15836EJ4V0UD 27 CHAPTER 2 PIN FUNCTIONS 2.1 Pin Function List There are two types of pin I/O buffer power supplies: AVREF and VDD. The relationship between these power supplies and the pins is shown below. Table 2-1. Pin I/O Buffer Power Supplies Power Supply AVREF VDD Corresponding Pins P20 to P23 Pins other than P20 to P23 (1) Port pins Pin Name P00 P01 P02 P03 P10 P11 P12 P13 P14 P15 P16 P17 P20 to P23 Input Port 2. 4-bit input-only port. P30 to P33 I/O Port 3. 4-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P120 I/O Port 12. 1-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P130 Output Port 13. 1-bit output-only port. Output - Input INTP0 Input INTP1 to INTP4 Input I/O I/O I/O Port 0. 4-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Port 1. 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input SCK10/TxD0 SI10/RxD0 SO10 TxD6 RxD6 TOH0 TOH1/INTP5 TI50/TO50 ANI0 to ANI3 Note Function After Reset Input Alternate Function TI000 TI010/TO00 - Note Note TxD0 and RxD0 are available only in the PD780102, 780103, and 78F0103. 28 User's Manual U15836EJ4V0UD CHAPTER 2 PIN FUNCTIONS (2) Non-port pins Pin Name INTP0 INTP1 to INTP4 INTP5 SI10 SO10 SCK10 RxD0 Note I/O Input Function External interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified After Reset Input Alternate Function P120 P30 to P33 P16/TOH1 Input Output I/O Input Serial data input to serial interface Serial data output from serial interface Clock input/output for serial interface Serial data input to asynchronous serial interface Input Input Input Input P11/RxD0 P12 P10/TxD0 P11/SI10 P14 Note Note RxD6 TxD0 TxD6 TI000 Input External count clock input to 16-bit timer/event counter 00 Capture trigger input to capture registers (CR000, CR010) of 16-bit timer/event counter 00 TI010 Capture trigger input to capture register (CR000) of 16-bit timer/event counter 00 TO00 TI50 TO50 TOH0 TOH1 ANI0 to ANI3 AVREF Input Input - Input Input - - - - - Positive power supply Ground potential Internally connected. Connect directly to VSS. Flash memory programming mode setting. High-voltage application for program write/verify. Connect to VSS in normal operation mode. Output Input Output Output 16-bit timer/event counter 00 output External count clock input to 8-bit timer/event counter 50 8-bit timer/event counter 50 output 8-bit timer H0 output 8-bit timer H1 output A/D converter analog input A/D converter reference voltage input and positive power supply for port 2 AVSS A/D converter ground potential. Make the same potential as VSS. RESET X1 X2 VDD VSS IC VPP System reset input Connecting resonator for X1 input clock - - - - - - - - Input - Input Input Input Input Input Note Output Serial data output from asynchronous serial interface Input P10/SCK10 P13 P00 P01/TO00 P01/TI010 P17/TO50 P17/TI50 P15 P16/INTP5 P20 to P23 - - - - - - - - - Note TxD0 and RxD0 are available only in the PD780102, 780103, and 78F0103. User's Manual U15836EJ4V0UD 29 CHAPTER 2 PIN FUNCTIONS 2.2 Description of Pin Functions 2.2.1 P00 to P03 (port 0) P00 to P03 function as a 4-bit I/O port. These pins also function as timer I/O. The following operation modes can be specified in 1-bit units. (1) Port mode P00 to P03 function as a 4-bit I/O port. P00 to P03 can be set to input or output in 1-bit units using port mode register 0 (PM0). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0). (2) Control mode P00 to P03 function as timer I/O. (a) TI000 This is the pins for inputting an external count clock to 16-bit timer/event counter 00 and is also for inputting a capture trigger signal to the capture registers (CR000, CR010) of 16-bit timer/event counter 00. (b) TI010 This is the pin for inputting a capture trigger signal to the capture register (CR000) of 16-bit timer/event counter 00. (c) TO00 This is a timer output pin. 2.2.2 P10 to P17 (port 1) P10 to P17 function as an 8-bit I/O port. These pins also function as pins for external interrupt request input, serial interface data I/O, clock I/O, and timer I/O. The following operation modes can be specified in 1-bit units. (1) Port mode P10 to P17 function as an 8-bit I/O port. P10 to P17 can be set to input or output in 1-bit units using port mode register 1 (PM1). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (PU1). (2) Control mode P10 to P17 function as external interrupt request input, serial interface data I/O, clock I/O, and timer I/O. (a) SI10 This is a serial data input pin of the serial interface. (b) SO10 This is a serial data output pin of the serial interface. (c) SCK10 This is a serial clock I/O pin of the serial interface. (d) RxD0Note, RxD6 These are the serial data input pins of the asynchronous serial interface. 30 User's Manual U15836EJ4V0UD CHAPTER 2 PIN FUNCTIONS (e) TxD0Note, TxD6 These are serial data output pins of the asynchronous serial interface. Note TxD0 and RxD0 are available only in the PD780102, 780103, and 78F0103. (f) TI50 This is the pin for inputting an external count clock to 8-bit timer/event counter 50. (g) TO50, TOH0, and TOH1 These are timer output pins. (h) INTP5 This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. 2.2.3 P20 to P23 (port 2) P20 to P23 function as a 4-bit input-only port. These pins also function as pins for A/D converter analog input. The following operation modes can be specified in 1-bit units. (1) Port mode P20 to P23 function as a 4-bit input-only port. (2) Control mode P20 to P23 function as A/D converter analog input pins (ANI0 to ANI3). When using these pins as analog input pins, see (5) ANI0/P20 to ANI3/P23 in 10.6 Cautions for A/D Converter. 2.2.4 P30 to P33 (port 3) P30 to P33 function as a 4-bit I/O port. These pins also function as pins for external interrupt request input. The following operation modes can be specified in 1-bit units. (1) Port mode P30 to P33 function as a 4-bit I/O port. P30 to P33 can be set to input or output in 1-bit units using port mode register 3 (PM3). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (PU3). (2) Control mode P30 to P33 function as external interrupt request input pins (INTP1 to INTP4) for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. 2.2.5 P120 (port 12) P120 functions as a 1-bit I/O port. This pin also functions as a pin for external interrupt request input. The following operation modes can be specified in 1-bit units. (1) Port mode P120 functions as a 1-bit I/O port. P120 can be set to input or output in 1-bit units using port mode register 12 (PM12). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12). User's Manual U15836EJ4V0UD 31 CHAPTER 2 PIN FUNCTIONS (2) Control mode P120 functions as an external interrupt request input pin (INTP0) for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. 2.2.6 P130 (port 13) P130 functions as a 1-bit output-only port. 2.2.7 AVREF This is the A/D converter reference voltage input pin. When A/D converter is not used, connect this pin directly to VDD. 2.2.8 AVSS This is the A/D converter ground potential pin. Even when the A/D converter is not used, always use this pin with the same potential as the VSS pin. 2.2.9 RESET This is the active-low system reset input pin. 2.2.10 X1 and X2 These are the pins for connecting a resonator for X1 input clock oscillation. When supplying an external clock, input a signal to the X1 pin and input the inverse signal to the X2 pin. 2.2.11 VDD This is the positive power supply pin. 2.2.12 VSS This is the ground potential pin. 2.2.13 VPP (flash memory versions only) This is a pin for flash memory programming mode setting and high-voltage application for program write/verify. Connect to VSS in the normal operation mode. 2.2.14 IC (mask ROM versions only) The IC (Internally Connected) pin is provided to set the test mode to check the 78K0/KB1 at shipment. Connect it directly to VSS with the shortest possible wire in the normal operation mode. When a potential difference is produced between the IC pin and the VSS pin because the wiring between these two pins is too long or external noise is input to the IC pin, the user's program may not operate normally. * Connect the IC pin directly to VSS. VSS IC As short as possible 32 User's Manual U15836EJ4V0UD CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-2 shows the types of pin I/O circuit and the recommended connections of unused pins. Refer to Figure 2-1 for the configuration of the I/O circuits of each type. Table 2-2. Pin I/O Circuit Types Pin Name P00/TI000 P01/TI010/TO00 P02 P03 P10/SCK10/TxD0 P11/SI10/RxD0 P12/SO10 P13/TxD6 P14/RxD6 P15/TOH0 P16/TOH1/INTP5 P17/TI50/TO50 P20/ANI0 to P23/ANI3 P30/INTP1 to P33/INTP4 9-C 8-A Input I/O Connect to VDD or VSS. Input: Independently connect to VSS via a resistor. 8-A 5-A 8-A Note I/O Circuit Type 8-A I/O I/O Input: Recommended Connection of Unused Pins Independently connect to VDD or VSS via a resistor. Output: Leave open. Note 5-A Output: Leave open. P120/INTP0 Input: Independently connect to VDD or VSS via a resistor. Output: Leave open. P130 RESET AVREF AVSS IC VPP Connect to VSS. 3-C 2 - Output Input Input - Connect directly to VDD. Connect directly to VSS. Leave open. - Note TxD0 and RxD0 are available only in the PD780102, 780103, and 78F0103. User's Manual U15836EJ4V0UD 33 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List Type 2 Type 8-A VDD Pull-up enable P-ch VDD IN Data Schmitt-triggered input with hysteresis characteristics Output disable P-ch IN/OUT N-ch Type 3-C Type 9-C VDD P-ch Data N-ch OUT IN P-ch N-ch AVSS VREF (threshold voltage) + - Comparator Input enable Type 5-A VDD Pull-up enable VDD Data P-ch P-ch IN/OUT Output disable N-ch Input enable 34 User's Manual U15836EJ4V0UD CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space Products in the 78K0/KB1 can each access a 64 KB memory space. Figures 3-1 to 3-4 show the memory maps. Caution Regardless of the internal memory capacity, the initial values of internal memory size switching register (IMS) of all products in the 78K0/KB1 are fixed (IMS = CFH). Therefore, set the value corresponding to each product as indicated below. Table 3-1. Internal Memory Size Switching Register (IMS) Set Value Internal Memory Size Switching Register (IMS) PD780101 PD780102 PD780103 PD78F0103 42H 04H 06H Value corresponding to mask ROM version User's Manual U15836EJ4V0UD 35 CHAPTER 3 CPU ARCHITECTURE Figure 3-1. Memory Map (PD780101) F F F FH Special function registers (SFR) 256 x 8 bits F F 0 0H F E F FH F E E 0H F E D FH General-purpose registers 32 x 8 bits Internal high-speed RAM 512 x 8 bits F D 0 0H F C F FH Data memory space 1 F F FH Program area 1 0 0 0H 0 F F FH CALLF entry area Reserved 0 8 0 0H 0 7 F FH Program area 0 0 8 0H 0 0 7 FH 2 0 0 0H 1 F F FH Program memory space 0 0 0 0H Internal ROM 8192 x 8 bits 0 0 4 0H 0 0 3 FH Vector table area 0 0 0 0H CALLT table area 36 User's Manual U15836EJ4V0UD CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map (PD780102) F F F FH Special function registers (SFR) 256 x 8 bits F F 0 0H F E F FH F E E 0H F E D FH General-purpose registers 32 x 8 bits Internal high-speed RAM 768 x 8 bits 3 F F FH Program area 1 0 0 0H 0 F F FH CALLF entry area 0 8 0 0H 0 7 F FH Program area 0 0 8 0H 0 0 7 FH 4 0 0 0H 3 F F FH Program memory space Internal ROM 16384 x 8 bits 0 0 4 0H 0 0 3 FH Vector table area 0 0 0 0H CALLT table area F C 0 0H F B F FH Data memory space Reserved 0 0 0 0H User's Manual U15836EJ4V0UD 37 CHAPTER 3 CPU ARCHITECTURE Figure 3-3. Memory Map (PD780103) F F F FH Special function registers (SFR) 256 x 8 bits F F 0 0H F E F FH F E E 0H F E D FH General-purpose registers 32 x 8 bits Internal high-speed RAM 768 x 8 bits F C 0 0H F B F FH Data memory space 5 F F FH Program area 1 0 0 0H 0 F F FH CALLF entry area 0 8 0 0H 0 7 F FH Program area 0 0 8 0H 0 0 7 FH 6 0 0 0H 5 F F FH Program memory space Internal ROM 24576 x 8 bits 0 0 4 0H 0 0 3 FH Vector table area 0 0 0 0H CALLT table area Reserved 0 0 0 0H 38 User's Manual U15836EJ4V0UD CHAPTER 3 CPU ARCHITECTURE Figure 3-4. Memory Map (PD78F0103) F F F FH Special function registers (SFR) 256 x 8 bits F F 0 0H F E F FH F E E 0H F E D FH General-purpose registers 32 x 8 bits Internal high-speed RAM 768 x 8 bits F C 0 0H F B F FH Data memory space 5 F F FH Program area 1 0 0 0H 0 F F FH CALLF entry area 0 8 0 0H 0 7 F FH Program area 0 0 8 0H 0 0 7 FH 6 0 0 0H 5 F F FH Program memory space Flash memory 24576 x 8 bits 0 0 4 0H 0 0 3 FH Vector table area 0 0 0 0H CALLT table area Reserved 0 0 0 0H User's Manual U15836EJ4V0UD 39 CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores the program and table data. Normally, it is addressed with the program counter (PC). 78K0/KB1 products incorporate internal ROM (mask ROM or flash memory), as shown below. Table 3-2. Internal ROM Capacity Part Number Structure Internal ROM Capacity 8192 x 8 bits (0000H to 1FFFH) 16384 x 8 bits (0000H to 3FFFH) 24576 x 8 bits (0000H to 5FFFH) Flash memory 24576 x 8 bits (0000H to 5FFFH) PD780101 PD780102 PD780103 PD78F0103 Mask ROM The internal program memory space is divided into the following areas. (1) Vector table area The 64-byte area 0000H to 003FH is reserved as a vector table area. The program start addresses for branch upon reset signal input or generation of each interrupt request are stored in the vector table area. Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses. Table 3-3. Vector Table Vector Table Address 0000H Interrupt Source RESET input, POC, LVI clock monitor, WDT Vector Table Address 0016H Interrupt Source INTST6 Note 0004H 0006H 0008H 000AH 000CH 000EH 0010H 0012H 0014H INTLVI INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTSRE6 INTSR6 0018H 001AH 001CH 001EH 0020H 0022H 0024H 0026H INTCSI10/INTST0 INTTMH1 INTTMH0 INTTM50 INTTM000 INTTM010 INTAD INTSR0 Note Note Available only in the PD780102, 780103, and 78F0103. (2) CALLT instruction table area The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT). (3) CALLF instruction entry area The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF). 40 User's Manual U15836EJ4V0UD CHAPTER 3 CPU ARCHITECTURE 3.1.2 Internal data memory space 78K0/KB1 products incorporate the following internal high-speed RAM. Table 3-4. Internal High-Speed RAM Capacity Part Number Internal High-Speed RAM 512 x 8 bits (FD00H to FEFFH) 768 x 8 bits (FC00H to FEFFH) PD780101 PD780102 PD780103 PD78F0103 The 32-byte area FEE0H to FEFFH is assigned to four general-purpose register banks consisting of eight 8-bit registers per bank. This area cannot be used as a program area in which instructions are written and executed. The internal high-speed RAM can also be used as a stack memory. 3.1.3 Special function register (SFR) area On-chip peripheral hardware special function registers (SFRs) are allocated in the area FF00H to FFFFH (refer to Table 3-5 Special Function Register List in 3.2.3 Special Function Registers (SFRs)). Caution Do not access addresses to which SFRs are not assigned. User's Manual U15836EJ4V0UD 41 CHAPTER 3 CPU ARCHITECTURE 3.1.4 Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the 78K0/KB1, based on operability and other considerations. For areas containing data memory in particular, special addressing methods designed for the functions of special function registers (SFR) and general-purpose registers are available for use. Figures 3-5 to 3-8 show the correspondence between data memory and addressing. For details of each addressing mode, refer to 3.4 Operand Address Addressing. Figure 3-5. Correspondence Between Data Memory and Addressing (PD780101) F F F FH Special function registers (SFR) 256 x 8 bits F F 2 0H F F 1 FH F F 0 0H F E F FH F E E 0H F E D FH General-purpose registers 32 x 8 bits Register addressing Short direct addressing SFR addressing Internal high-speed RAM 512 x 8 bits F E 2 0H F E 1 FH F D 0 0H F C F FH Direct addressing Register indirect addressing Based addressing Based indexed addressing Reserved 2 0 0 0H 1 F F FH Internal ROM 8192 x 8 bits 0 0 0 0H 42 User's Manual U15836EJ4V0UD CHAPTER 3 CPU ARCHITECTURE Figure 3-6. Correspondence Between Data Memory and Addressing (PD780102) F F F FH Special function registers (SFR) 256 x 8 bits F F 2 0H F F 1 FH F F 0 0H F E F FH F E E 0H F E D FH General-purpose registers 32 x 8 bits Register addressing Short direct addressing SFR addressing Internal high-speed RAM 768 x 8 bits F E 2 0H F E 1 FH Direct addressing Register indirect addressing Based addressing Based indexed addressing Reserved F C 0 0H F B F FH 4 0 0 0H 3 F F FH Internal ROM 16384 x 8 bits 0 0 0 0H User's Manual U15836EJ4V0UD 43 CHAPTER 3 CPU ARCHITECTURE Figure 3-7. Correspondence Between Data Memory and Addressing (PD780103) F F F FH Special function registers (SFR) 256 x 8 bits F F 2 0H F F 1 FH F F 0 0H F E F FH F E E 0H F E D FH General-purpose registers 32 x 8 bits Register addressing Short direct addressing SFR addressing Internal high-speed RAM 768 x 8 bits F E 2 0H F E 1 FH Direct addressing Register indirect addressing Based addressing Based indexed addressing Reserved F C 0 0H F B F FH 6 0 0 0H 5 F F FH Internal ROM 24576 x 8 bits 0 0 0 0H 44 User's Manual U15836EJ4V0UD CHAPTER 3 CPU ARCHITECTURE Figure 3-8. Correspondence Between Data Memory and Addressing (PD78F0103) F F F FH Special function registers (SFR) 256 x 8 bits F F 2 0H F F 1 FH F F 0 0H F E F FH F E E 0H F E D FH General-purpose registers 32 x 8 bits Register addressing Short direct addressing SFR addressing Internal high-speed RAM 768 x 8 bits F E 2 0H F E 1 FH Direct addressing Register indirect addressing Based addressing Based indexed addressing Reserved F C 0 0H F B F FH 6 0 0 0H 5 F F FH Flash memory 24576 x 8 bits 0 0 0 0H User's Manual U15836EJ4V0UD 45 CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers 78K0/KB1 products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP). (1) Program counter (PC) The program counter is a 16-bit register that holds the address information of the next program to be executed. In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be fetched. When a branch instruction is executed, immediate data and register contents are set. RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter. Figure 3-9. Format of Program Counter 15 PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 0 PC0 (2) Program status word (PSW) The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are reset upon execution of the RETB, RETI and POP PSW instructions. RESET input sets the PSW to 02H. Figure 3-10. Format of Program Status Word 7 PSW IE Z RBS1 AC RBS0 0 ISP 0 CY 46 User's Manual U15836EJ4V0UD CHAPTER 3 CPU ARCHITECTURE (a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledgment operations of the CPU. When 0, the IE flag is set to the interrupt disabled (DI) state, and maskable interrupt requests are all disabled. When 1, the IE flag is set to the interrupt enabled (EI) state and interrupt request acknowledgment enable is controlled with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources and a priority specification flag. The IE flag is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI instruction execution. (b) Zero flag (Z) When the operation result is zero, this flag is set (1). It is reset (0) in all other cases. (c) Register bank select flags (RBS0 and RBS1) These are 2-bit flags to select one of the four register banks. In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction execution is stored. (d) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases. (e) In-service priority flag (ISP) This flag manages the priority of acknowledgeable maskable vectored interrupts. When this flag is 0, lowlevel vectored interrupt requests specified by a priority specification flag register (PR0L, PR0H, PR1L) (refer to 14.3 (3) Priority specification flag registers (PR0L, PR0H, PR1L)) can not be acknowledged. Actual request acknowledgment is controlled by the interrupt enable flag (IE). (f) Carry flag (CY) This flag stores on overflow or underflow upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution. (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. User's Manual U15836EJ4V0UD 47 CHAPTER 3 CPU ARCHITECTURE Figure 3-11. Format of Stack Pointer 15 SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 0 SP0 The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restore) from the stack memory. Each stack operation saves/restores data as shown in Figures 3-12 and 3-13. Caution Since RESET input makes the SP contents undefined, be sure to initialize the SP before use. Figure 3-12. Data to Be Saved to Stack Memory (a) PUSH rp instruction (when SP = FEE0H) SP FEE0H FEE0H FEDFH Register pair upper Register pair lower SP FEDEH FEDEH (b) CALL, CALLF, CALLT instructions (when SP = FEE0H) SP FEE0H FEE0H FEDFH PC15-PC8 PC7-PC0 SP FEDEH FEDEH (c) Interrupt, BRK instructions (when SP = FEE0H) SP FEE0H FEE0H FEDFH FEDEH PSW PC15-PC8 PC7-PC0 SP FEDDH FEDDH 48 User's Manual U15836EJ4V0UD CHAPTER 3 CPU ARCHITECTURE Figure 3-13. Data to Be Restored from Stack Memory (a) POP rp instruction (when SP = FEDEH) SP FEE0H FEE0H FEDFH Register pair upper Register pair lower SP FEDEH FEDEH (b) RET instruction (when SP = FEDEH) SP FEE0H FEE0H FEDFH PC15-PC8 PC7-PC0 SP FEDEH FEDEH (c) RETI, RETB instructions (when SP = FEDDH) SP FEE0H FEE0H FEDFH FEDEH PSW PC15-PC8 PC7-PC0 SP FEDDH FEDDH User's Manual U15836EJ4V0UD 49 CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX, BC, DE, and HL). These registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute names (R0 to R7 and RP0 to RP3). Register banks to be used for instruction execution are set by the CPU control instruction (SEL RBn). Because of the 4-register bank configuration, an efficient program can be created by switching between a register for normal processing and a register for interrupts for each bank. Figure 3-14. Configuration of General-Purpose Registers (a) Absolute name 16-bit processing FEFFH R7 BANK0 FEF8H RP3 R6 R5 BANK1 FEF0H RP1 R2 R1 BANK3 FEE0H 15 0 7 0 RP0 R0 RP2 R4 R3 BANK2 FEE8H 8-bit processing (b) Function name 16-bit processing FEFFH H BANK0 FEF8H HL L D BANK1 FEF0H BC C A BANK3 FEE0H 15 0 7 0 AX X DE E B BANK2 FEE8H 8-bit processing 50 User's Manual U15836EJ4V0UD CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special Function Registers (SFRs) Unlike a general-purpose register, each special function register has a special function. SFRs are allocated to the FF00H to FFFFH area. Special function registers can be manipulated like general-purpose registers, using operation, transfer and bit manipulation instructions. The manipulatable bit units, 1, 8, and 16, depend on the special function register type. Each manipulation bit unit can be specified as follows. * 1-bit manipulation Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). This manipulation can also be specified with an address. * 8-bit manipulation Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). This manipulation can also be specified with an address. * 16-bit manipulation Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (sfrp). When specifying an address, describe an even address. Table 3-5 gives a list of the special function registers. The meanings of items in the table are as follows. * Symbol Symbol indicating the address of a special function register. It is a reserved word in the RA78K0, and is defined by the header file "sfrbit.h" in the CC78K0. When using the RA78K0, ID78K0-NS, ID78K0, or SM78K0, symbols can be written as an instruction operand. * R/W Indicates whether the corresponding special function register can be read or written. R/W: Read/write enable R: W: Read only Write only * Manipulatable bit units Indicates the manipulatable bit unit (1, 8, or 16). "-" indicates a bit unit for which manipulation is not possible. * After reset Indicates each register status upon RESET input. User's Manual U15836EJ4V0UD 51 CHAPTER 3 CPU ARCHITECTURE Table 3-5. Special Function Register List (1/3) Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit 1 Bit FF00H FF01H FF02H FF03H FF08H FF09H FF0AH FF0BH FF0CH FF0DH FF0FH FF10H FF11H FF12H FF13H FF14H FF15H FF16H FF17H FF18H FF19H FF1AH FF1BH FF20H FF21H FF23H FF28H FF29H FF2AH FF2BH FF2CH FF30H FF31H FF33H FF3CH FF48H FF49H FF4FH 8-bit timer counter 50 8-bit timer compare register 50 8-bit timer H compare register 00 8-bit timer H compare register 10 8-bit timer H compare register 01 8-bit timer H compare register 11 Port mode register 0 Port mode register 1 Port mode register 3 A/D converter mode register Analog input channel specification register Power-fail comparison mode register Power-fail comparison threshold register Port mode register 12 Pull-up resistor option register 0 Pull-up resistor option register 1 Pull-up resistor option register 3 Pull-up resistor option register 12 External interrupt rising edge enable register External interrupt falling edge enable register Input switch control register TM50 CR50 CMP00 CMP10 CMP01 CMP11 PM0 PM1 PM3 ADM ADS PFM PFT PM12 PU0 PU1 PU3 PU12 EGP EGN ISC R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - - - - - - - - - - - - - - - - - - - - - - - - - - - - 00H 00H 00H 00H 00H 00H FFH FFH FFH 00H 00H 00H 00H FFH 00H 00H 00H 00H 00H 00H 00H 16-bit timer capture/compare register 010 CR010 R/W - - 0000H 16-bit timer capture/compare register 000 CR000 R/W - - 0000H Receive buffer register 6 Transmit buffer register 6 Port register 12 Port register 13 Serial I/O shift register 10 16-bit timer counter 00 RXB6 TXB6 P12 P13 SIO10 TM00 R R/W R/W R/W R R - - - - - - - - - - FFH FFH 00H 00H 00H 0000H Port register 0 Port register 1 Port register 2 Port register 3 A/D conversion result register P0 P1 P2 P3 ADCR R/W R/W R R/W R - 8 Bits - 16 Bits - - - - After Reset 00H 00H Undefined 00H Undefined 52 User's Manual U15836EJ4V0UD CHAPTER 3 CPU ARCHITECTURE Table 3-5. Special Function Register List (2/3) Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit 1 Bit FF50H Asynchronous serial interface operation mode register 6 FF53H Asynchronous serial interface reception error status register 6 FF55H Asynchronous serial interface transmission status register 6 FF56H FF57H FF58H FF69H FF6AH FF6BH FF6CH FF70H Clock selection register 6 Baud rate generator control register 6 Asynchronous serial interface control register 6 8-bit timer H mode register 0 Timer clock selection register 50 8-bit timer mode control register 50 8-bit timer H mode register 1 Asynchronous serial interface operation mode register 0 FF71H FF72H FF73H Note 1 Note 1 After Reset 01H 8 Bits 16 Bits - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ASIM6 R/W - - - - - - - - - - - - - - ASIS6 R 00H ASIF6 R 00H CKSR6 BRGC6 ASICL6 TMHMD0 TCL50 TMC50 TMHMD1 ASIM0 R/W R/W R/W R/W R/W R/W R/W R/W 00H FFH 16H 00H 00H 00H 00H 01H Baud rate generator control register 0 Receive buffer register 0 Note 1 Note 1 BRGC0 RXB0 ASIS0 R/W R R 1FH FFH 00H Asynchronous serial interface reception error status register 0 Note 1 FF74H FF80H FF81H FF84H FF98H FF99H FFA0H FFA1H FFA2H FFA3H Transmit shift register 0 TXS0 CSIM10 CSIC10 SOTB10 WDTM WDTE RCM MCM MOC OSTC W R/W R/W R/W R/W R/W R/W R/W R/W R FFH 00H 00H Undefined 67H 9AH 00H 00H 00H 00H Serial operation mode register 10 Serial clock selection register 10 Transmit buffer register 10 Watchdog timer mode register Watchdog timer enable register Ring-OSC mode register Main clock mode register Main OSC control register Oscillation stabilization time counter status register FFA4H FFA9H FFACH FFBAH FFBBH Oscillation stabilization time select register Clock monitor mode register Reset control flag register 16-bit timer mode control register 00 Prescaler mode register 00 OSTS CLM RESF TMC00 PRM00 R/W R/W R R/W R/W 05H 00H 00H Note 2 00H 00H Notes 1. 2. PD780102, 780103, and 78F0103 only. This value varies depending on the reset source. User's Manual U15836EJ4V0UD 53 CHAPTER 3 CPU ARCHITECTURE Table 3-5. Special Function Register List (3/3) Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit 1 Bit FFBCH FFBDH FFBEH FFBFH FFE0H FFE1H FFE2H FFE4H FFE5H FFE6H FFE8H FFE9H FFEAH FFF0H FFFBH Capture/compare control register 00 16-bit timer output control register 00 Low-voltage detection register Low-voltage detection level selection register Interrupt request flag register 0L Interrupt request flag register 0H Interrupt request flag register 1L Interrupt mask flag register 0L Interrupt mask flag register 0H Interrupt mask flag register 1L Priority specification flag register 0L Priority specification flag register 0H Priority specification flag register 1L Internal memory size switching register Processor clock control register Note After Reset 00H 00H 00H 00H 00H 00H - 00H FFH FFH - FFH FFH FFH - - - FFH CFH 00H 8 Bits 16 Bits - - - - CRC00 TOC00 LVIM LVIS IF0 IF0L IF0H IF1L MK0 R/W R/W R/W R/W R/W R/W R/W MK0L R/W MK0H R/W - - MK1L PR0 R/W PR0L R/W PR0H R/W PR1L IMS PCC R/W R/W R/W Note The default value of IMS is fixed (IMS = CFH) in all products in the 78K0/KB1 regardless of the internal memory capacity. Therefore, set the following value to each product. Internal Memory Size Switching Register (IMS) PD780101 PD780102 PD780103 PD78F0103 42H 04H 06H Value corresponding to mask ROM version 54 User's Manual U15836EJ4V0UD CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. When a branch instruction is executed, the branch destination information is set to the PC and branched by the following addressing (for details of instructions, refer to 78K/0 Series Instructions User's Manual (U12326E)). 3.3.1 Relative addressing [Function] The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (PC) and branched. displacement value is treated as signed two's complement data (-128 to +127) and bit 7 becomes a sign bit. In other words, relative addressing consists of relative branching from the start address of the following instruction to the -128 to +127 range. This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed. [Illustration] 15 PC + 15 8 7 S jdisp8 15 PC 0 6 0 0 ... PC indicates the start address of the instruction after the BR instruction. The When S = 0, all bits of are 0. When S = 1, all bits of are 1. User's Manual U15836EJ4V0UD 55 CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space. The CALLF !addr11 instruction is branched to the 0800H to 0FFFH area. [Illustration] In the case of CALL !addr16 and BR !addr16 instructions 7 CALL or BR Low Addr. High Addr. 0 15 PC 87 0 In the case of CALLF !addr11 instruction 76 fa10-8 fa7-0 4 3 CALLF 0 15 PC 0 0 0 0 11 10 1 87 0 56 User's Manual U15836EJ4V0UD CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. This function is carried out when the CALLT [addr5] instruction is executed. This instruction references the address stored in the memory table from 40H to 7FH, and allows branching to the entire memory space. [Illustration] 7 Operation code 1 6 1 5 ta4-0 1 0 1 15 Effective address 0 0 0 0 0 0 0 8 0 7 0 6 1 5 10 0 7 Memory (Table) Low Addr. 0 Effective address+1 High Addr. 15 PC 8 7 0 3.3.4 Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration] 7 rp A 0 7 X 0 15 PC 8 7 0 User's Manual U15836EJ4V0UD 57 CHAPTER 3 CPU ARCHITECTURE 3.4 Operand Address Addressing The following methods are available to specify the register and memory (addressing) to undergo manipulation during instruction execution. 3.4.1 Implied addressing [Function] The register that functions as an accumulator (A and AX) among the general-purpose registers is automatically (implicitly) addressed. Of the 78K0/KB1 instruction words, the following instructions employ implied addressing. Instruction MULU DIVUW ADJBA/ADJBS ROR4/ROL4 Register to Be Specified by Implied Addressing A register for multiplicand and AX register for product storage AX register for dividend and quotient storage A register for storage of numeric values that become decimal correction targets A register for storage of digit data that undergoes digit rotation [Operand format] Because implied addressing can be automatically employed with an instruction, no particular operand format is necessary. [Description example] In the case of MULU X With an 8-bit x 8-bit multiply instruction, the product of A register and X register is stored in AX. In this example, the A and AX registers are specified by implied addressing. 58 User's Manual U15836EJ4V0UD CHAPTER 3 CPU ARCHITECTURE 3.4.2 Register addressing [Function] The general-purpose register to be specified is accessed as an operand with the register bank select flags (RBS0 to RBS1) and the register specify codes (Rn and RPn) of an operation code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code. [Operand format] Identifier r rp Description X, A, C, B, E, D, L, H AX, BC, DE, HL `r' and `rp' can be described by absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL). [Description example] MOV A, C; when selecting C register as r Operation code 0 1 1 0 0 0 1 0 Register specify code INCW DE; when selecting DE register pair as rp Operation code 1 0 0 0 0 1 0 0 Register specify code User's Manual U15836EJ4V0UD 59 CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an operand address. [Operand format] Identifier addr16 Description Label or 16-bit immediate data [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code 1 0 0 0 1 1 1 0 OP code 0 0 0 0 0 0 0 0 00H 1 1 1 1 1 1 1 0 FEH [Illustration] 7 OP code addr16 (lower) addr16 (upper) 0 Memory 60 User's Manual U15836EJ4V0UD CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. Internal RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively. The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the overall SFR area. Ports that are frequently accessed in a program and compare and capture registers of the timer/event counter are mapped in this area, allowing SFRs to be manipulated with a small number of bytes and clocks. When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is cleared to 0. When it is at 00H to 1FH, bit 8 is set to 1. Refer to the [Illustration]. [Operand format] Identifier saddr saddrp Description Immediate data that indicate label or FE20H to FF1FH Immediate data that indicate label or FE20H to FF1FH (even address only) [Description example] MOV 0FE30H, A; when transferring value of A register to saddr (FE30H) Operation code 1 1 1 1 0 0 1 0 OP code 0 0 1 1 0 0 0 0 30H (saddr-offset) [Illustration] 7 OP code saddr-offset 0 Short direct memory 15 Effective address 1 1 1 1 1 1 1 87 0 When 8-bit immediate data is 20H to FFH, = 0 When 8-bit immediate data is 00H to 1FH, = 1 User's Manual U15836EJ4V0UD 61 CHAPTER 3 CPU ARCHITECTURE 3.4.5 Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing. [Operand format] Identifier sfr sfrp Description Special function register name 16-bit manipulatable special function register name (even address only) [Description example] MOV PM0, A; when selecting PM0 (FF20H) as sfr Operation code 1 1 1 1 0 1 1 0 OP code 0 0 1 0 0 0 0 0 20H (sfr-offset) [Illustration] 7 OP code sfr-offset 0 SFR 15 Effective address 1 1 1 1 1 1 1 87 1 0 62 User's Manual U15836EJ4V0UD CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] Register pair contents specified by a register pair specify code in an instruction word and by a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing can be carried out for all the memory spaces. [Operand format] Identifier - [DE], [HL] Description [Description example] MOV A, [DE]; when selecting [DE] as register pair Operation code 1 0 0 0 0 1 0 1 [Illustration] 16 DE D 87 E The memory address specified with the register pair DE 0 7 The contents of the memory addressed are transferred. 7 A 0 Memory 0 User's Manual U15836EJ4V0UD 63 CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces. [Operand format] Identifier - [HL + byte] Description [Description example] MOV A, [HL + 10H]; when setting byte to 10H Operation code 1 0 1 0 1 1 1 0 0 0 0 1 0 0 0 0 [Illustration] 16 HL H 87 L +10 0 7 The contents of the memory addressed are transferred. 7 A 0 Memory 0 64 User's Manual U15836EJ4V0UD CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] The B or C register contents specified in an instruction word are added to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory. Addition is performed by expanding the B or C register contents as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces. [Operand format] Identifier - [HL + B], [HL + C] Description [Description example] In the case of MOV A, [HL + B] (selecting B register) Operation code 1 0 1 0 1 0 1 1 [Illustration] 16 HL H + 7 B 0 8 7 L 0 7 The contents of the memory addressed are transferred. 7 A 0 Memory 0 User's Manual U15836EJ4V0UD 65 CHAPTER 3 CPU ARCHITECTURE 3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and return instructions are executed or the register is saved/reset upon generation of an interrupt request. With stack addressing, only the internal high-speed RAM area can be accessed. [Description example] In the case of PUSH DE (saving DE register) Operation code 1 0 1 1 0 1 0 1 [Illustration] 7 SP FEE0H FEE0H FEDFH SP FEDEH FEDEH D E Memory 0 66 User's Manual U15836EJ4V0UD CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions There are two types of pin I/O buffer power supplies: AVREF and VDD. The relationship between these power supplies and the pins is shown below. Table 4-1. Pin I/O Buffer Power Supplies Power Supply AVREF VDD Corresponding Pins P20 to P23 Pins other than P20 to P23 78K0/KB1 products are provided with the ports shown in Figure 4-1, which enable variety of control operations. The functions of each port are shown in Table 4-2. In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the alternate functions, refer to CHAPTER 2 PIN FUNCTIONS. Figure 4-1. Port Types P20 Port 2 P23 P30 Port 3 P33 P00 Port 0 P03 P10 Port 1 Port 12 Port 13 P120 P130 P17 User's Manual U15836EJ4V0UD 67 CHAPTER 4 PORT FUNCTIONS Table 4-2. Port Functions Pin Name P00 P01 P02 P03 P10 P11 P12 P13 P14 P15 P16 P17 P20 to P23 I/O I/O I/O Port 0. 4-bit I/O port. Function After Reset Input Alternate Function TI000 TI010/TO00 - Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Port 1. 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input SCK10/TxD0 SI10/RxD0 SO10 TxD6 RxD6 TOH0 TOH1/INTP5 TI50/TO50 Note Note Input Port 2. 4-bit input-only port. Input ANI0 to ANI3 P30 to P33 I/O Port 3. 4-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input INTP1 to INTP4 P120 I/O Port 12. 1-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input INTP0 P130 Output Port 13. 1-bit output-only port. Output - Note TxD0 and RxD0 are available only in the PD780102, 780103, and 78F0103. 4.2 Port Configuration A port includes the following hardware. Table 4-3. Port Configuration Item Control registers Configuration Port mode register (PM0, PM1, PM3, PM12) Port register (P0 to P3, P12, P13) Pull-up resistor option register (PU0, PU1, PU3, PU12) Port Pull-up resistors Total: 22 (CMOS I/O: 17, CMOS input: 4, CMOS output: 1) Total: 17 (software control only) 68 User's Manual U15836EJ4V0UD CHAPTER 4 PORT FUNCTIONS 4.2.1 Port 0 Port 0 is a 4-bit I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (PM0). When the P00 to P03 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 0 (PU0). This port can also be used for timer I/O. RESET input sets port 0 to input mode. Figures 4-2 to 4-4 show block diagrams of port 0. Figure 4-2. Block Diagram of P00 VDD WRPU PU0 PU00 P-ch Alternate function RD Internal bus WRPORT Output latch (P00) WRPM PM0 PM00 Selector P00/TI000 PU0: PM0: RD: Pull-up resistor option register 0 Port mode register 0 Read signal WRxx: Write signal User's Manual U15836EJ4V0UD 69 CHAPTER 4 PORT FUNCTIONS Figure 4-3. Block Diagram of P01 VDD WRPU PU0 PU01 P-ch Alternate function RD Internal bus WRPORT Output latch (P01) WRPM PM0 PM01 Selector P01/TI010/TO00 Alternate function PU0: PM0: RD: Pull-up resistor option register 0 Port mode register 0 Read signal WRxx: Write signal 70 User's Manual U15836EJ4V0UD CHAPTER 4 PORT FUNCTIONS Figure 4-4. Block Diagram of P02 and P03 VDD WRPU PU0 PU02, PU03 P-ch RD Internal bus WRPORT Output latch (P02, P03) WRPM PM0 PM02, PM03 Selector P02, P03 PU0: PM0: RD: Pull-up resistor option register 0 Port mode register 0 Read signal WRxx: Write signal User's Manual U15836EJ4V0UD 71 CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 1 Port 1 is an 8-bit I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 1 (PU1). This port can also be used for external interrupt request input, serial interface data I/O, clock I/O, and timer I/O. RESET input sets port 1 to input mode. Figures 4-5 to 4-9 show block diagrams of port 1. Caution When using P10/SCK10 (/TxD0Note), P11/SI10 (/RxD0Note), and P12/SO10 as general-purpose ports, do not write to serial clock selection register 10 (CSIC10). Figure 4-5. Block Diagram of P10 VDD WRPU PU1 PU10 P-ch Alternate function RD Internal bus WRPORT Output latch (P10) WRPM PM1 PM10 Selector P10/SCK10 (/TxD0Note) Alternate function Note Available only in the PD780102, 780103, and 78F0103. PU1: PM1: RD: Pull-up resistor option register 1 Port mode register 1 Read signal WRxx: Write signal 72 User's Manual U15836EJ4V0UD CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P11 and P14 VDD WRPU PU1 PU11, PU14 P-ch Alternate function RD Internal bus WRPORT Output latch (P11, P14) WRPM PM1 PM11, PM14 Selector P11/SI10 (/RxD0Note), P14/RxD6 Note Available only in the PD780102, 780103, and 78F0103. PU1: PM1: RD: Pull-up resistor option register 1 Port mode register 1 Read signal WRxx: Write signal User's Manual U15836EJ4V0UD 73 CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P12 and P15 VDD WRPU PU1 PU12, PU15 RD P-ch Internal bus WRPORT Output latch (P12, P15) WRPM PM1 PM12, PM15 Selector P12/SO10, P15/TOH0 Alternate function PU1: PM1: RD: Pull-up resistor option register 1 Port mode register 1 Read signal WRxx: Write signal 74 User's Manual U15836EJ4V0UD CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of P13 VDD WRPU PU1 PU13 RD P-ch Internal bus WRPORT Output latch (P13) WRPM PM1 PM13 Selector P13/TxD6 Alternate function PU1: PM1: RD: Pull-up resistor option register 1 Port mode register 1 Read signal WRxx: Write signal User's Manual U15836EJ4V0UD 75 CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of P16 and P17 VDD WRPU PU1 PU16, PU17 P-ch Alternate function RD Internal bus WRPORT Output latch (P16, P17) WRPM PM1 PM16, PM17 Selector P16/TOH1/INTP5, P17/TI50/TO50 Alternate function PU1: PM1: RD: Pull-up resistor option register 1 Port mode register 1 Read signal WRxx: Write signal 76 User's Manual U15836EJ4V0UD CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 2 Port 2 is a 4-bit input-only port. This port can also be used for A/D converter analog input. Figure 4-10 shows a block diagram of port 2. Figure 4-10. Block Diagram of P20 to P23 RD Internal bus A/D converter P20/ANI0 to P23/ANI3 RD: Read signal User's Manual U15836EJ4V0UD 77 CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 3 Port 3 is a 4-bit I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (PM3). When the P30 to P33 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 3 (PU3). This port can also be used for external interrupt request input. RESET input sets port 3 to input mode. Figure 4-11 shows a block diagram of port 3. Figure 4-11. Block Diagram of P30 to P33 VDD WRPU PU3 PU30 to PU33 P-ch Alternate function RD Internal bus WRPORT Output latch (P30 to P33) WRPM PM3 PM30 to PM33 Selector P30/INTP1 to P33/INTP4 PU3: PM3: RD: Pull-up resistor option register 3 Port mode register 3 Read signal WRxx: Write signal 78 User's Manual U15836EJ4V0UD CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 12 Port 12 is a 1-bit I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units using port mode register 12 (PM12). When the P120 pin is used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12). This port can also be used for external interrupt input. RESET input sets port 12 to input mode. Figure 4-12 shows a block diagram of port 12. Figure 4-12. Block Diagram of P120 VDD WRPU PU12 PU120 P-ch Alternate function RD Internal bus WRPORT Output latch (P120) WRPM PM12 PM120 Selector P120/INTP0 PU12: RD: Pull-up resistor option register 12 Read signal PM12: Port mode register 12 WRxx: Write signal User's Manual U15836EJ4V0UD 79 CHAPTER 4 PORT FUNCTIONS 4.2.6 Port 13 Port 13 is a 1-bit output-only port. Figure 4-13 shows a block diagram of port 13. Figure 4-13. Block Diagram of P130 RD Internal bus WRPORT Output latch (P130) P130 RD: Read signal WRxx: Write signal Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level immediately after reset is released, the output signal of P130 can be dummy-output as the reset signal to the CPU. 4.3 Registers Controlling Port Function Port functions are controlled by the following three types of registers. * Port mode registers (PM0, PM1, PM3, PM12) * Port registers (P0 to P3, P12, P13) * Pull-up resistor option registers (PU0, PU1, PU3, PU12) (1) Port mode registers (PM0, PM1, PM3, and PM12) These registers specify input or output mode for the port in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets these registers to FFH. When port pins are used as alternate-function pins, set the port mode register and output latch as shown in Table 4-3. 80 User's Manual U15836EJ4V0UD CHAPTER 4 PORT FUNCTIONS Figure 4-14. Format of Port Mode Register Symbol PM0 7 1 6 1 5 1 4 1 3 PM03 2 PM02 1 PM01 0 PM00 Address After reset FF20H FFH R/W R/W PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 FF21H FFH R/W PM3 1 1 1 1 PM33 PM32 PM31 PM30 FF23H FFH R/W PM12 1 1 1 1 1 1 1 PM120 FF2CH FFH R/W PMmn Pmn pin I/O mode selection (m = 0, 1, 3, 12; n = 0 to 7) 0 1 Output mode (output buffer on) Input mode (output buffer off) Table 4-4. Settings of Port Mode Register and Output Latch When Alternate Function Is Used Pin Name Alternate Function Name P00 P01 TI000 TI010 TO00 P10 SCK10 Input Input Output Input Output TxD0 P11 SI10 RxD0 P12 P13 P14 P15 P16 Note Note PMxx I/O 1 1 0 1 0 0 1 1 0 0 1 0 0 1 1 0 1 1 Pxx x x 0 x 1 1 x x 0 1 x 0 0 x x 0 x x Output Input Input Output Output Input Output Output Input Input Output Input Input SO10 TxD6 RxD6 TOH0 TOH1 INTP5 P17 TI50 TO50 P30 to P33 P120 INTP1 to INTP4 INTP0 Note TxD0 and RxD0 are available only in the PD780102, 780103, and 78F0103. Remark x: Pxx: Don't care Port output latch PMxx: Port mode register User's Manual U15836EJ4V0UD 81 CHAPTER 4 PORT FUNCTIONS (2) Port registers (P0 to P3, P12, P13) These registers write the data that is output from the chip when data is output from a port. If the data is read in the input mode, the pin level is read. If it is read in the output mode, the value of the output latch is read. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears these registers to 00H (but P2 is undefined). Figure 4-15. Format of Port Register Symbol P0 7 0 7 P1 P17 7 P2 0 7 P3 0 7 P12 0 7 P13 0 6 0 6 P16 6 0 6 0 6 0 6 0 5 0 5 P15 5 0 5 0 5 0 5 0 4 0 4 P14 4 0 4 0 4 0 4 0 3 P03 3 P13 3 P23 3 P33 3 0 3 0 2 P02 2 P12 2 P22 2 P32 2 0 2 0 1 P01 1 P11 1 P21 1 P31 1 0 1 0 0 P00 0 P10 0 P20 0 P30 0 P120 0 P130 FF0DH 00H (output latch) R/W FF0CH 00H (output latch) R/W FF03H 00H (output latch) R/W FF02H Undefined R FF01H 00H (output latch) R/W Address FF00H After reset 00H (output latch) R/W R/W Pmn m = 0 to 3, 12, 13; n = 0 to 7 Output data control (in output mode) Input data read (in input mode) Input low level Input high level 0 1 Output 0 Output 1 82 User's Manual U15836EJ4V0UD CHAPTER 4 PORT FUNCTIONS (3) Pull-up resistor option registers (PU0, PU1, PU3, and PU12) These registers specify whether the on-chip pull-up resistors of P00 to P03, P10 to P17, P30 to P33, or P120 is to be used or not. An on-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode of the pins to which the use of an on-chip pull-up resistor has been specified. On-chip pull-up resistor cannot be connected for bits set to output mode and bits used as alternate-function output pins, regardless of the settings of PU0, PU1, PU3 and PU12. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears these registers to 00H. Figure 4-16. Format of Pull-up Resistor Option Register Symbol PU0 7 0 7 PU1 PU17 7 PU3 0 7 PU12 0 6 0 6 PU16 6 0 6 0 5 0 5 PU15 5 0 5 0 4 0 4 PU14 4 0 4 0 3 PU03 3 PU13 3 PU33 3 0 2 PU02 2 PU12 2 PU32 2 0 1 PU01 1 PU11 1 PU31 1 0 0 PU00 0 PU10 0 PU30 0 PU120 FF3CH 00H R/W FF33H 00H R/W FF31H 00H R/W Address After reset FF30H 00H R/W R/W PUmn Pmn pin on-chip pull-up resistor selection (m = 0, 1, 3, 12; n = 0 to 7) 0 1 On-chip pull-up resistor not connected On-chip pull-up resistor connected User's Manual U15836EJ4V0UD 83 CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. Caution In the case of a 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined, even for bits other than the manipulated bit. 4.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. Once data is written to the output latch, it is retained until data is written to the output latch again. The data of the output latch is cleared by reset. (2) Input mode A value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not change. Once data is written to the output latch, it is retained until data is written to the output latch again. 4.4.2 Reading from I/O port (1) Output mode The output latch contents are read by a transfer instruction. The output latch contents do not change. (2) Input mode The pin status is read by a transfer instruction. The output latch contents do not change. 4.4.3 Operations on I/O port (1) Output mode An operation is performed on the output latch contents, and the result is written to the output latch. The output latch contents are output from the pins. Once data is written to the output latch, it is retained until data is written to the output latch again. The data of the output latch is cleared by reset. (2) Input mode The pin level is read and an operation is performed on its contents. The result of the operation is written to the output latch, but since the output buffer is off, the pin status does not change. 84 User's Manual U15836EJ4V0UD CHAPTER 5 CLOCK GENERATOR 5.1 Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two system clock oscillators are available. * X1 oscillator The X1 oscillator oscillates a clock of fXP = 2.0 to 10.0 MHz. Oscillation can be stopped by executing the STOP instruction or setting the main OSC control register (MOC). * Ring-OSC oscillator The Ring-OSC oscillator oscillates a clock of fR = 240 kHz (TYP.). Oscillation can be stopped by setting the Ring-OSC mode register (RCM) when "Can be stopped by software" is set by a mask option and the X1 input clock is used as the CPU clock. Remarks 1. fXP: X1 input clock oscillation frequency 2. fR: Ring-OSC clock oscillation frequency 5.2 Configuration of Clock Generator The clock generator includes the following hardware. Table 5-1. Configuration of Clock Generator Item Control registers Processor clock control register (PCC) Ring-OSC mode register (RCM) Main clock mode register (MCM) Main OSC control register (MOC) Oscillation stabilization time counter status register (OSTC) Oscillation stabilization time select register (OSTS) Oscillator X1 oscillator Ring-OSC oscillator Configuration User's Manual U15836EJ4V0UD 85 CHAPTER 5 CLOCK GENERATOR Figure 5-1. Block Diagram of Clock Generator Internal bus Main OSC control register (MOC) STOP MSTOP Main clock mode register (MCM) MCS MCM0 Oscillation stabilization time select register (OSTS) OSTS2 OSTS1 OSTS0 3 X1 oscillation stabilization time counter Oscillation MOST MOST MOST MOST MOST stabilization 11 13 14 15 16 time counter status register (OSTC) X1 X1 oscillator X2 fXP fX Operation clock switch fX 2 Ring-OSC oscillator Prescaler fX 22 fX 23 fX 24 Control signal Controller Processor clock control register (PCC) PCC2 PCC1 PCC0 C P U CPU clock (fCPU) 3 Selector fCPU fR Prescaler Clock to peripheral hardware Mask option 1: Cannot be stopped 0. Can be stopped RSTOP Ring-OSC mode register (RCM) Internal bus Prescaler 8-bit timer H1, watchdog timer 86 User's Manual U15836EJ4V0UD CHAPTER 5 CLOCK GENERATOR 5.3 Registers Controlling Clock Generator The following six registers are used to control the clock generator. * Processor clock control register (PCC) * Ring-OSC mode register (RCM) * Main clock mode register (MCM) * Main OSC control register (MOC) * Oscillation stabilization time counter status register (OSTC) * Oscillation stabilization time select register (OSTS) (1) Processor clock control register (PCC) This register sets the division ratio of the CPU clock. PCC can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 5-2. Format of Processor Clock Control Register (PCC) Address: FFFBH Symbol PCC 7 0 After reset: 00H 6 0 R/W 5 0 4 0 3 0 2 PCC2 1 PCC1 0 PCC0 PCC2 PCC1 PCC0 CPU clock selection (fCPU) MCM0 = 0 MCM0 = 1 fXP fXP/2 2 0 0 0 0 1 0 0 1 1 0 Other than above 0 1 0 1 0 fX fX/2 fX/2 fX/2 fX/2 2 fR fR/2 fR/2 fR/2 fR/2 fXP/2 fXP/2 fXP/2 2 3 3 3 4 4 4 Setting prohibited Remarks 1. MCM0: Bit 0 of the main clock mode register (MCM) 2. fX: Main system clock oscillation frequency (X1 input clock oscillation frequency or Ring-OSC clock oscillation frequency) 3. fR: Ring-OSC clock oscillation frequency 4. fXP: X1 input clock oscillation frequency User's Manual U15836EJ4V0UD 87 CHAPTER 5 CLOCK GENERATOR The fastest instruction can be executed in 2 clocks of the CPU clock in the 78K0/KB1. Therefore, the relationship between the CPU clock (fCPU) and minimum instruction execution time is as shown in the Table 5-2. Table 5-2. Relationship Between CPU Clock and Minimum Instruction Execution Time CPU Clock (fCPU) Note Minimum Instruction Execution Time: 2/fCPU X1 Input Clock (at 10 MHz Operation) 0.2 s 0.4 s 0.8 s 1.6 s 3.2 s Ring-OSC Clock (at 240 kHz (TYP.) Operation) 8.3 s (TYP.) 16.6 s (TYP.) 33.2 s (TYP.) 66.4 s (TYP.) 132.8 s (TYP.) fX fX/2 fX/2 fX/2 fX/2 2 3 4 Note The main clock mode register (MCM) is used to set the CPU clock (X1 input clock/Ring-OSC clock) (see Figure 5-4). (2) Ring-OSC mode register (RCM) This register sets the operation mode of Ring-OSC. This register is valid when "Can be stopped by software" is set for Ring-OSC by a mask option, and the X1 input clock is input to the CPU clock. If "Cannot be stopped" is selected for Ring-OSC by a mask option, settings for this register are invalid. RCM can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 5-3. Format of Ring-OSC Mode Register (RCM) Address: FFA0H Symbol RCM 7 0 After reset: 00H 6 0 R/W 5 0 4 0 3 0 2 0 1 0 <0> RSTOP RSTOP 0 1 Ring-OSC oscillating Ring-OSC stopped Ring-OSC oscillating/stopped Caution Make sure that bit 1 (MCS) of the main clock mode register (MCM) is 1 before setting RSTOP. 88 User's Manual U15836EJ4V0UD CHAPTER 5 CLOCK GENERATOR (3) Main clock mode register (MCM) This register sets the CPU clock (X1 input clock/Ring-OSC clock). MCM can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 5-4. Format of Main Clock Mode Register (MCM) Address: FFA1H Symbol MCM 7 0 After reset: 00H 6 0 R/W Note 5 0 4 0 3 0 2 0 <1> MCS <0> MCM0 MCS 0 1 Operates with Ring-OSC clock Operates with X1 input clock CPU clock status MCM0 0 1 Ring-OSC clock X1 input clock Selection of clock supplied to CPU Note Bit 1 is read-only. Caution When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the divided clock of the Ring-OSC oscillator output (fX) is supplied to the peripheral hardware (fX = 240 kHz (TYP.)). Operation of the peripheral hardware with the Ring-OSC clock cannot be guaranteed. Therefore, when the Ring-OSC clock is selected as the clock supplied to the CPU, do not use peripheral hardware. In addition, stop the peripheral hardware before switching the clock supplied to the CPU from the X1 input clock to the Ring-OSC clock. Note, however, that the following peripheral hardware can be used when the CPU operates on the Ring-OSC clock. * Watchdog timer * Clock monitor * 8-bit timer H1 when fR/27 is selected as the count clock * Peripheral hardware with an external clock selected as the clock source (Except when the external count clock of TM00 is selected (TI000 valid edge)) User's Manual U15836EJ4V0UD 89 CHAPTER 5 CLOCK GENERATOR (4) Main OSC control register (MOC) This register selects the operation mode of the X1 input clock. This register is used to stop the X1 oscillator operation when the CPU is operating with the Ring-OSC clock. Therefore, this register is valid only when the CPU is operating with the Ring-OSC clock. MOC can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 5-5. Format of Main OSC Control Register (MOC) Address: FFA2H Symbol MOC After reset: 00H <7> MSTOP 6 0 R/W 5 0 4 0 3 0 2 0 1 0 0 0 MSTOP 0 1 X1 oscillator operating X1 oscillator stopped Control of X1 oscillator operation Caution Make sure that bit 1 (MCS) of the main clock mode register (MCM) is 0 before setting MSTOP. 90 User's Manual U15836EJ4V0UD CHAPTER 5 CLOCK GENERATOR (5) Oscillation stabilization time counter status register (OSTC) This is the status register of the X1 input clock oscillation stabilization time counter. If the Ring-OSC clock is used as the CPU clock, the X1 input clock oscillation stabilization time can be checked. OSTC can be read by a 1-bit or 8-bit memory manipulation instruction. When reset is released (reset by RESET input, POC, LVI, clock monitor, and WDT), the STOP instruction, MSTOP = 1 clear OSTC to 00H. Figure 5-6. Format of Oscillation Stabilization Time Counter Status Register (OSTC) Address: FFA3H Symbol OSTC 7 0 After reset: 00H 6 0 R 5 0 4 MOST11 3 MOST13 2 MOST14 1 MOST15 0 MOST16 MOST11 1 1 1 1 1 MOST13 0 1 1 1 1 MOST14 0 0 1 1 1 MOST15 0 0 0 1 1 MOST16 0 0 0 0 1 Oscillation stabilization time status 2 /fXP min. (204.8 s min.) 11 2 /fXP min. (819.2 s min.) 13 2 /fXP min. (1.64 ms min.) 2 /fXP min. (3.27 ms min.) 2 /fXP min. (6.55 ms min.) 16 15 14 Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST11 and remain 1. 2. If the STOP mode is entered and then released while the Ring-OSC clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS The X1 oscillation stabilization time counter counts up to the oscillation stabilization time set by OSTS. Note, therefore, that only the status up to the oscillation stabilization time set by OSTS is set to OSTC after STOP mode is released. 3. The wait time when STOP mode is released does not include the time after STOP mode release until clock oscillation starts ("a" below) regardless of whether STOP mode is released by RESET input or interrupt generation. STOP mode release X1 pin voltage waveform a Remarks 1. Values in parentheses are reference values for operation with fXP = 10 MHz. 2. fXP: X1 input clock oscillation frequency User's Manual U15836EJ4V0UD 91 CHAPTER 5 CLOCK GENERATOR (6) Oscillation stabilization time select register (OSTS) This register is used to select the X1 oscillation stabilization wait time when STOP mode is released. The wait time set by OSTS is valid only after STOP mode is released with the X1 input clock selected as the CPU clock. After STOP mode is released with Ring-OSC selected as the CPU clock, the oscillation stabilization time must be confirmed by OSTC. OSTS can be set by an 8-bit memory manipulation instruction. RESET input sets OSTS to 05H. Figure 5-7. Format of Oscillation Stabilization Time Select Register (OSTS) Address: FFA4H Symbol OSTS 7 0 After reset: 05H 6 0 R/W 5 0 4 0 3 0 2 OSTS2 1 OSTS1 0 OSTS0 OSTS2 0 0 0 1 1 OSTS1 0 1 1 0 0 Other than above OSTS0 1 0 1 0 1 11 Oscillation stabilization time selection 2 /fXP (204.8 s) 2 /fXP (819.2 s) 13 2 /fXP (1.64 ms) 2 /fXP (3.27 ms) 2 /fXP (6.55 ms) Setting prohibited 16 15 14 Cautions 1. If the STOP mode is entered and then released while the Ring-OSC clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS The X1 oscillation stabilization time counter counts up to the oscillation stabilization time set by OSTS. Note, therefore, that only the status up to the oscillation stabilization time set by OSTS is set to OSTC after STOP mode is released. 2. The wait time when STOP mode is released does not include the time after STOP mode release until clock oscillation starts ("a" below) regardless of whether STOP mode is released by RESET input or interrupt generation. STOP mode release X1 pin voltage waveform a Remarks 1. Values in parentheses are reference values for operation with fXP = 10 MHz. 2. fXP: X1 input clock oscillation frequency 92 User's Manual U15836EJ4V0UD CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillator 5.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator (Standard: 10 MHz) connected to the X1 and X2 pins. An external clock can be input to the X1 oscillator. In this case, input the clock signal to the X1 pin and input the inverse signal to the X2 pin. Figure 5-8 shows the external circuit of the X1 oscillator. Figure 5-8. External Circuit of X1 Oscillator (a) Crystal, ceramic oscillation VSS X1 (b) External clock External clock X1 X2 Crystal resonator or ceramic resonator X2 Caution When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the Figure 5-9 to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. Figure 5-9 shows examples of incorrect resonator connection. User's Manual U15836EJ4V0UD 93 CHAPTER 5 CLOCK GENERATOR Figure 5-9. Examples of Incorrect Resonator Connection (a) Too long wiring (b) Crossed signal line PORT VSS X1 X2 VSS X1 X2 (c) Wiring near high alternating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) VDD Pmn VSS X1 X2 High current VSS X1 X2 A B High current C (e) Signals are fetched VSS X1 X2 94 User's Manual U15836EJ4V0UD CHAPTER 5 CLOCK GENERATOR 5.4.2 Ring-OSC oscillator A Ring-OSC oscillator is incorporated in the 78K0/KB1. "Can be stopped by software" or "Cannot be stopped" can be selected by a mask option. The Ring-OSC clock always oscillates after RESET release (240 kHz (TYP.)). 5.4.3 Prescaler The prescaler generates various clocks by dividing the X1 oscillator output when the X1 input clock is selected as the clock to be supplied to the CPU. Caution When the Ring-OSC clock is selected as the clock supplied to the CPU, the prescaler generates various clocks by dividing the Ring-OSC oscillator output (fX = 240 kHz (TYP.)). 5.5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode. * X1 input clock fXP * Ring-OSC clock fR * CPU clock fCPU * Clock to peripheral hardware The CPU starts operation when the on-chip Ring-OSC oscillator starts outputting after reset release in the 78K0/KB1, thus enabling the following. (1) Enhancement of security function When the X1 input clock is set as the CPU clock by the default setting, the device cannot operate if the X1 input clock is damaged or badly connected and therefore does not operate after reset is released. However, the start clock of the CPU is the on-chip Ring-OSC clock, so the device can be started by the Ring-OSC clock after reset release by the clock monitor (detection of X1 input clock stop). Consequently, the system can be safely shut down by performing a minimum operation, such as acknowledging a reset source by software or performing safety processing when there is a malfunction. User's Manual U15836EJ4V0UD 95 CHAPTER 5 CLOCK GENERATOR (2) Improvement of performance Because the CPU can be started without waiting for the X1 input clock oscillation stabilization time, the total performance can be improved. A timing diagram of the CPU default start using Ring-OSC is shown in Figure 5-10. Figure 5-10. Timing Diagram of CPU Default Start Using Ring-OSC X1 input clock (fXP) Ring-OSC clock (fR) RESET Switched by software CPU clock Operation stopped: 17/fR Ring-OSC clock X1 input clock X1 oscillation stabilization time: 211/fXP to 216/fXPNote Note Check using the oscillation stabilization time counter status register (OSTC). (a) When the RESET signal is generated, bit 0 of the main clock mode register (MCM) is set to 0 and the RingOSC clock is set as the CPU clock. However, a clock is supplied to the CPU after 17 clocks of the Ring-OSC clock have elapsed after RESET release (or clock supply to the CPU stops for 17 clocks). During the RESET period, oscillation of the X1 input clock and Ring-OSC clock is stopped. (b) After RESET release, the CPU clock can be switched from the Ring-OSC clock to the X1 input clock using bit 0 (MCM0) of the main clock mode register (MCM) after the X1 input clock oscillation stabilization time has elapsed. At this time, check the oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) before switching the CPU clock. The CPU clock status can be checked using bit 1 (MCS) of MCM. (c) Ring-OSC can be set to stopped/oscillating using the Ring-OSC mode register (RCM) when "Can be stopped by software" is selected for the Ring-OSC by a mask option, if the X1 input is used as the CPU clock. Make sure that MCS is 1 at this time. (d) When Ring-OSC is used as the CPU clock, the X1 input clock can be set to stopped/oscillating using the main OSC control register (MOC). Make sure that MCS is 0 at this time. (e) Select the X1 input clock oscillation stabilization time (211/fXP, 213/fXP, 214/fXP, 215/fXP, 216/fXP) using the oscillation stabilization time select register (OSTS) when releasing STOP mode while the X1 input clock is being used as the CPU clock. In addition, when releasing STOP mode while RESET is released and the Ring-OSC clock is being used as the CPU clock, check the X1 input clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC). 96 User's Manual U15836EJ4V0UD CHAPTER 5 CLOCK GENERATOR A status transition diagram of this product is shown in Figure 5-11, and the relationship between the operation clocks in each operation status and between the oscillation control flag and oscillation status of each clock are shown in Tables 5-3 and 5-4, respectively. Figure 5-11. Status Transition Diagram (1/2) (1) When "Ring-OSC can be stopped by software" is selected by mask option HALTNote 4 Interrupt Interrupt HALT instruction Status 4 RSTOP = 0 CPU clock: fXP fXP: Oscillating fR: Oscillation stopped RSTOP = 1Note 1 Status 3 CPU clock: fXP fXP: Oscillating fR: Oscillating Interrupt HALT instruction MCM0 = 0 MCM0 = 1Note 2 HALT instruction HALT instruction Interrupt Status 2 CPU clock: fR fXP: Oscillating fR: Oscillating MSTOP = 1Note 3 Status 1 CPU clock: fR fXP: Oscillation stopped fR: Oscillating MSTOP = 0 Interrupt STOP instruction STOP instruction Interrupt STOP instruction STOP instruction Interrupt Interrupt STOPNote 4 Reset release ResetNote 5 Notes 1. 2. When shifting from status 3 to status 4, make sure that bit 1 (MCS) of the main clock mode register (MCM) is 1. Before shifting from status 2 to status 3 after reset and STOP are released, check the X1 input clock oscillation stabilization time status using the oscillation stabilization time counter status register (OSTC). 3. 4. When shifting from status 2 to status 1, make sure that MCS is 0. When "Ring-OSC can be stopped by software" is selected by a mask option, the watchdog timer stops operating in the HALT and STOP modes, regardless of the source clock of the watchdog timer. However, oscillation of Ring-OSC does not stop even in the HALT and STOP modes if RSTOP = 0. 5. All reset sources (RESET input, POC, LVI, clock monitor, and WDT) User's Manual U15836EJ4V0UD 97 CHAPTER 5 CLOCK GENERATOR Figure 5-11. Status Transition Diagram (2/2) (2) When "Ring-OSC cannot be stopped" is selected by mask option HALT Interrupt Interrupt HALT instruction HALT instruction Interrupt HALT instruction Status 3 CPU clock: fXP fXP: Oscillating fR: Oscillating MCM0 = 0 MCM0 = 1Note 1 Status 2 CPU clock: fR fXP: Oscillating fR: Oscillating MSTOP = 1Note 2 MSTOP = 0 STOP instruction Status 1 CPU clock: fR fXP: Oscillation stopped fR: Oscillating Interrupt STOP instruction STOP instruction Interrupt Interrupt STOPNote 3 Reset release ResetNote 4 Notes 1. Before shifting from status 2 to status 3 after reset and STOP are released, check the X1 input clock oscillation stabilization time status using the oscillation stabilization time counter status register (OSTC). 2. 3. When shifting from status 2 to status 1, make sure that MCS is 0. The watchdog timer operates using Ring-OSC even in STOP mode if "Ring-OSC cannot be stopped" is selected by a mask option. Ring-OSC division can be selected as the count source of 8-bit timer H1 (TMH1), so clear the watchdog timer using the TMH1 interrupt request before watchdog timer overflow. If this processing is not performed, an internal reset signal is generated at watchdog timer overflow after STOP instruction execution. 4. All reset sources (RESET input, POC, LVI, clock monitor, and WDT) 98 User's Manual U15836EJ4V0UD CHAPTER 5 CLOCK GENERATOR Table 5-3. Relationship Between Operation Clocks in Each Operation Status Status X1 Oscillator Ring-OSC Oscillator CPU Clock After Operation Mode Reset STOP HALT Oscillating Stopped Note 1 Note 2 RSTOP = 0 Stopped Oscillating Oscillating Stopped RSTOP = 1 Ring-OSC Note 3 Note 4 Stopped Stopped Ring-OSC X1 Release Prescaler Clock Supplied to Peripherals MCM0 = 0 MCM0 = 1 Notes 1. 2. 3. 4. When "Cannot be stopped" is selected for Ring-OSC by a mask option. When "Can be stopped by software" is selected for Ring-OSC by a mask option. Operates using the CPU clock at STOP instruction execution. Operates using the CPU clock at HALT instruction execution. Caution The RSTOP setting is valid only when "Can be stopped by software" is set for Ring-OSC by a mask option. Remark RSTOP: Bit 0 of the Ring-OSC mode register (RCM) MCM0: Bit 0 of the main clock mode register (MCM) Table 5-4. Oscillation Control Flags and Clock Oscillation Status X1 Oscillator MSTOP = 1 RSTOP = 0 RSTOP = 1 MSTOP = 0 RSTOP = 0 RSTOP = 1 Stopped Setting prohibited Oscillating Oscillating Stopped Ring-OSC Oscillator Oscillating Caution The RSTOP setting is valid only when "Can be stopped by software" is set for Ring-OSC by a mask option. Remark MSTOP: Bit 7 of the main OSC control register (MOC) RSTOP: Bit 0 of the Ring-OSC mode register (RCM) User's Manual U15836EJ4V0UD 99 CHAPTER 5 CLOCK GENERATOR 5.6 Time Required to Switch Between Ring-OSC Clock and X1 Input Clock Bit 0 (MCM0) of the main clock mode register (MCM) is used to switch between the Ring-OSC clock and X1 input clock. In the actual switching operation, switching does not occur immediately after MCM0 rewrite; several instructions are executed using the pre-switch over clock after switching MCM0 (see Table 5-5). Bit 1 (MCS) of MCM is used to judge that operation is performed using either the Ring-OSC clock or X1 input clock. To stop the original clock after changing the clock, wait for the number of clocks shown in Table 5-5. Table 5-5. Time Required to Switch Between Ring-OSC Clock and X1 Input Clock PCC PCC2 0 0 0 0 1 PCC1 0 0 1 1 0 PCC0 0 1 0 1 0 fXP/fR + 1 clock fXP/2fR + 1 clock fXP/4fR + 1 clock fXP/8fR + 1 clock fXP/16fR + 1 clock Time Required for Switching X1Ring-OSC Ring-OSCX1 2 clocks Caution To calculate the maximum time, set fR = 120 kHz. Remarks 1. PCC: Processor clock control register 2. fXP: X1 input clock oscillation frequency 3. fR: Ring-OSC clock oscillation frequency 4. The maximum time is the number of clocks of the CPU clock before switching. 5.7 Time Required for CPU Clock Switchover The CPU clock can be switched using bits 0 to 2 (PCC0 to PCC2) of the processor clock control register (PCC). The actual switchover operation is not performed immediately after rewriting to the PCC; operation continues on the pre-switchover clock for several instructions (see Table 5-6). Table 5-6. Maximum Time Required for CPU Clock Switchover Set Value Before Switchover PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 8 clocks 4 clocks 2 clocks 1 clock 4 clocks 2 clocks 1 clock 2 clocks 1 clock 1 clock 0 0 0 0 16 clocks 1 0 1 16 clocks 8 clocks 0 0 1 16 clocks 8 clocks 4 clocks 1 1 0 16 clocks 8 clocks 4 clocks 2 clocks 0 Set Value After Switchover Remark The maximum time is the number of clocks of the CPU clock before switching. 100 User's Manual U15836EJ4V0UD CHAPTER 5 CLOCK GENERATOR 5.8 Clock Switching Flowchart and Register Setting 5.8.1 Switching from Ring-OSC clock to X1 input clock Figure 5-12. Switching from Ring-OSC Clock to X1 Input Clock (Flowchart) After reset release Register initial value after reset PCC = 00H RCM = 00H MCM = 00H MOC = 00H OSTC = 00H OSTS = 05HNote ; fCPU = fR ; Ring-OSC oscillation ; Ring-OSC clock operation ; X1 oscillation ; Oscillation stabilization time status register ; Oscillation stabilization time fXP/216 Each processing OSTC checkNote X1 oscillation stabilization time has not elapsed ; X1 oscillation stabilization time status check Ring-OSC clock operation X1 oscillation stabilization time has elapsed PCC setting Ring-OSC clock operation (dividing set PCC) MCM.0 1 MCM.1 (MCS) is changed from 0 to 1 X1 input clock operation X1 input clock operation Note Check the oscillation stabilization wait time of the X1 oscillator after reset release using the OSTC register and then switch to the X1 input clock operation after the oscillation stabilization wait time has elapsed. The OSTS register setting is valid only after STOP mode is released by interrupt during X1 input clock operation. User's Manual U15836EJ4V0UD 101 CHAPTER 5 CLOCK GENERATOR 5.8.2 Switching from X1 input clock to Ring-OSC clock Figure 5-13. Switching from X1 Input Clock to Ring-OSC Clock (Flowchart) Register setting in X1 input clock operation MCM = 03H ; X1 input clock operation Yes: RSTOP = 1 X1 input clock operation RCM.0Note (RSTOP) = 1? ; Ring-OSC oscillating? No: RSTOP = 0 RSTOP = 0 MCM0 0 ; Ring-OSC clock operation MCM.1 (MCS) is changed from 1 to 0 Ring-OSC clock operation Ring-OSC clock operation Note Required only when "can be stopped by software" is selected for Ring-OSC by a mask option. 102 User's Manual U15836EJ4V0UD CHAPTER 5 CLOCK GENERATOR 5.8.3 Register settings The table below shows the statuses of the setting flags and status flags when each mode is set. Table 5-7. Clock and Register Settings fCPU Mode MCM Register MCM0 X1 input clock Note 2 Setting Flag MOC Register MSTOP 0 0 0 1 RCM Register RSTOP 0 1 0 0 Note 1 Status Flag MCM Register MCS 1 1 0 0 Ring-OSC oscillating Ring-OSC stopped 1 1 0 0 Ring-OSC clock X1 oscillating X1 stopped Notes 1. 2. This is valid only when "can be stopped by software" is selected for Ring-OSC by mask option. Do not set MSTOP to 1 during X1 input clock operation (oscillation of X1 is not stopped even when MSTOP = 1). User's Manual U15836EJ4V0UD 103 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.1 Functions of 16-Bit Timer/Event Counter 00 16-bit timer/event counter 00 has the following functions. * Interval timer * PPG output * Pulse width measurement * External event counter * Square-wave output * One-shot pulse output (1) Interval timer 16-bit timer/event counter 00 generates an interrupt request at the preset time interval. (2) PPG output 16-bit timer/event counter 00 can output a rectangular wave whose frequency and output pulse width can be set freely. (3) Pulse width measurement 16-bit timer/event counter 00 can measure the pulse width of an externally input signal. (4) External event counter 16-bit timer/event counter 00 can measure the number of pulses of an externally input signal. (5) Square-wave output 16-bit timer/event counter 00 can output a square wave with any selected frequency. (6) One-shot pulse output 16-bit timer/event counter 00 can output a one-shot pulse whose output pulse width can be set freely. 104 User's Manual U15836EJ4V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.2 Configuration of 16-Bit Timer/Event Counter 00 16-bit timer/event counter 00 includes the following hardware. Table 6-1. Configuration of 16-Bit Timer/Event Counter 00 Item Timer counter Register Timer input Timer output Control registers 16 bits (TM00) 16-bit timer capture/compare register: 16 bits (CR000, CR010) TI000, TI010 TO00, output controller 16-bit timer mode control register 00 (TMC00) Capture/compare control register 00 (CRC00) 16-bit timer output control register 00 (TOC00) Prescaler mode register 00 (PRM00) Port mode register 0 (PM0) Port register 0 (P0) Configuration Figure 6-1 shows the block diagram. Figure 6-1. Block Diagram of 16-Bit Timer/Event Counter 00 Internal bus Capture/compare control register 00 (CRC00) CRC002CRC001 CRC000 Selector INTTM000 Selector TI010/TO00/P01 Noise eliminator 16-bit timer capture/compare register 000 (CR000) Match Selector fX fX/22 fX/28 16-bit timer counter 00 (TM00) Match Clear Output controller Output latch (P01) PM01 TO00/TI010/ P01 fX Noise eliminator 2 Noise eliminator 16-bit timer capture/compare register 010 (CR010) Selector TI000/P00 INTTM010 CRC002 PRM001 PRM000 Prescaler mode register 00 (PRM00) TMC003 TMC002 TMC001 OVF00 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 16-bit timer output 16-bit timer mode control register 00 control register 00 (TOC00) (TMC00) Internal bus User's Manual U15836EJ4V0UD 105 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (1) 16-bit timer counter 00 (TM00) TM00 is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the input clock. Figure 6-2. Format of 16-Bit Timer Counter 00 (TM00) Address: FF10H, FF11H Symbol After reset: 0000H FF11H R FF10H TM00 The count value is reset to 0000H in the following cases. <1> At RESET input <2> If TMC003 and TMC002 are cleared <3> If the valid edge of TI000 is input in the mode in which clear & start occurs when inputting the valid edge of TI000 <4> If TM00 and CR000 match in the mode in which clear & start occurs on a match of TM00 and CR000 <5> OSPT00 is set in one-shot pulse output mode (2) 16-bit timer capture/compare register 000 (CR000) CR000 is a 16-bit register that has the functions of both a capture register and a compare register. Whether it is used as a capture register or as a compare register is set by bit 0 (CRC000) of capture/compare control register 00 (CRC00). CR000 can be set by a 16-bit memory manipulation instruction. RESET input clears CR000 to 0000H. Figure 6-3. Format of 16-Bit Timer Capture/Compare Register 000 (CR000) Address: FF12H, FF13H Symbol CR000 After reset: 0000H FF13H R/W FF12H * When CR000 is used as a compare register The value set in CR000 is constantly compared with the 16-bit timer counter 00 (TM00) count value, and an interrupt request (INTTM000) is generated if they match. The set value is held until CR000 is rewritten. * When CR000 is used as a capture register It is possible to select the valid edge of the TI000 pin or the TI010 pin as the capture trigger. The TI000 or TI010 pin valid edge is set using prescaler mode register 00 (PRM00) (see Table 6-2). 106 User's Manual U15836EJ4V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Table 6-2. CR000 Capture Trigger and Valid Edges of TI000 and TI010 Pins (1) TI000 pin valid edge selected as capture trigger (CRC001 = 1, CRC000 = 1) CR000 Capture Trigger TI000 Pin Valid Edge ES001 Falling edge Rising edge No capture operation Rising edge Falling edge Both rising and falling edges 0 0 1 ES000 1 0 1 (2) TI010 pin valid edge selected as capture trigger (CRC001 = 0, CRC000 = 1) CR000 Capture Trigger TI010 Pin Valid Edge ES101 Falling edge Rising edge Both rising and falling edges Falling edge Rising edge Both rising and falling edges 0 0 1 ES100 0 1 1 Remarks 1. Setting ES001, ES000 = 1, 0 and ES101, ES100 = 1, 0 is prohibited. 2. ES001, ES000: ES101, ES100: Bits 5 and 4 of prescaler mode register 00 (PRM00) Bits 7 and 6 of prescaler mode register 00 (PRM00) CRC001, CRC000: Bits 1 and 0 of capture/compare control register 00 (CRC00) Cautions 1. Set a value other than 0000H in CR000 in the mode in which clear & start occurs on a match of TM00 and CR000. However, in the free-running mode and in the clear mode using the valid edge of TI000, if CR000 is set to 0000H, an interrupt request (INTTM000) is generated when the value of CR000 changes from 0000H to 0001H following overflow (FFFFH). 2. When P01 is used as the valid edge input pin of TI010, it cannot be used as the timer output (TO00). Moreover, when P01 is used as TO00, it cannot be used as the valid edge input pin of TI010. 3. When CR000 is used as a capture register, read data is undefined if the register read time and capture trigger input conflict (the capture data itself is the correct value). If count stop input and capture trigger input conflict, the captured data is undefined. 4. Do not rewrite CR000 during TM00 operation. User's Manual U15836EJ4V0UD 107 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) 16-bit timer capture/compare register 010 (CR010) CR010 is a 16-bit register that has the functions of both a capture register and a compare register. Whether it is used as a capture register or a compare register is set by bit 2 (CRC002) of capture/compare control register 00 (CRC00). CR010 can be set by a 16-bit memory manipulation instruction. RESET input clears CR010 to 0000H. Figure 6-4. Format of 16-Bit Timer Capture/Compare Register 010 (CR010) Address: FF14H, FF15H Symbol After reset: 0000H FF15H R/W FF14H CR010 * When CR010 is used as a compare register The value set in the CR010 is constantly compared with the 16-bit timer counter 00 (TM00) count value, and an interrupt request (INTTM010) is generated if they match. The set value is held until CR010 is rewritten. * When CR010 is used as a capture register It is possible to select the valid edge of the TI000 pin as the capture trigger. The TI000 valid edge is set by prescaler mode register 00 (PRM00) (see Table 6-3). Table 6-3. CR010 Capture Trigger and Valid Edge of TI000 Pin (CRC002 = 1) CR010 Capture Trigger TI000 Pin Valid Edge ES001 Falling edge Rising edge Both rising and falling edges Falling edge Rising edge Both rising and falling edges 0 0 1 ES000 0 1 1 Remarks 1. Setting ES001, ES000 = 1, 0 is prohibited. 2. ES001, ES000: Bits 5 and 4 of prescaler mode register 00 (PRM00) CRC002: Bit 2 of capture/compare control register 00 (CRC00) Cautions 1. If the CR010 register is cleared to 0000H, an interrupt request (INTTM010) is generated after the TM00 register overflows, after the timer is cleared and started on a match between the TM00 register and the CR000 register, or after the timer is cleared by the valid edge of TI000 or a one-shot trigger. 2. When CR010 is used as a capture register, read data is undefined if the register read time and capture trigger input conflict (the capture data itself is the correct value). If count stop input and capture trigger input conflict, the captured data is undefined. 3. CR010 can be rewritten during TM00 operation. For details, see Caution 2 in Figure 6-15. 108 User's Manual U15836EJ4V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.3 Registers Controlling 16-Bit Timer/Event Counter 00 The following six registers are used to control 16-bit timer/event counter 00. * 16-bit timer mode control register 00 (TMC00) * Capture/compare control register 00 (CRC00) * 16-bit timer output control register 00 (TOC00) * Prescaler mode register 00 (PRM00) * Port mode register 0 (PM0) * Port register 0 (P0) (1) 16-bit timer mode control register 00 (TMC00) This register sets the 16-bit timer operating mode, the 16-bit timer counter 00 (TM00) clear mode, and output timing, and detects an overflow. TMC00 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears TMC00 to 00H. Caution 16-bit timer counter 00 (TM00) starts operation at the moment TMC002 and TMC003 are set to values other than 0, 0 (operation stop mode), respectively. Clear TMC002 and TMC003 to 0, 0 to stop operation. User's Manual U15836EJ4V0UD 109 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-5. Format of 16-Bit Timer Mode Control Register 00 (TMC00) Address FFBAH Symbol TMC00 7 0 6 0 After reset: 00H 5 0 4 0 R/W 3 2 1 <0> TMC003 TMC002 TMC001 OVF00 TMC003 TMC002 TMC001 Operating mode and clear mode selection TO00 inversion timing selection No change Interrupt request generation Not generated 0 0 0 0 0 1 0 1 0 Operation stop (TM00 cleared to 0) Free-running mode Match between TM00 and CR000 or match between TM00 and CR010 Generated on match between TM00 and CR000, or match between TM00 and CR010 0 1 1 Match between TM00 and CR000, match between TM00 and CR010 or TI000 valid edge - 1 1 1 0 0 1 0 1 0 Clear & start occurs on TI000 valid edge Clear & start occurs on match Match between TM00 and between TM00 and CR000 CR000 or match between TM00 and CR010 1 1 1 Match between TM00 and CR000, match between TM00 and CR010 or TI000 valid edge OVF00 0 1 Overflow not detected Overflow detected 16-bit timer counter 00 (TM00) overflow detection Cautions 1. Timer operation must be stopped before writing to bits other than the OVF00 flag. 2. Set the valid edge of the TI000/P00 pin using prescaler mode register 00 (PRM00). 3. If any of the following modes: the mode in which clear & start occurs on match between TM00 and CR000, the mode in which clear & start occurs at the TI00 valid edge, or freerunning mode is selected, when the set value of CR000 is FFFFH and the TM00 value changes from FFFFH to 0000H, the OVF00 flag is set to 1. Remark TO00: TI000: TM00: 16-bit timer/event counter 00 output pin 16-bit timer/event counter 00 input pin 16-bit timer counter 00 CR000: 16-bit timer capture/compare register 000 CR010: 16-bit timer capture/compare register 010 110 User's Manual U15836EJ4V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (2) Capture/compare control register 00 (CRC00) This register controls the operation of the 16-bit timer capture/compare registers (CR000, CR010). CRC00 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears CRC00 to 00H. Figure 6-6. Format of Capture/Compare Control Register 00 (CRC00) Address: FFBCH Symbol CRC00 7 0 After reset: 00H 6 0 R/W 5 0 4 0 3 0 2 CRC002 1 CRC001 0 CRC000 CRC002 0 1 CR010 operating mode selection Operates as compare register Operates as capture register CRC001 0 1 CR000 capture trigger selection Captures on valid edge of TI010 Captures on valid edge of TI000 by reverse phase CRC000 0 1 CR000 operating mode selection Operates as compare register Operates as capture register Cautions 1. Timer operation must be stopped before setting CRC00. 2. When the mode in which clear & start occurs on a match between TM00 and CR000 is selected with 16-bit timer mode control register 00 (TMC00), CR000 should not be specified as a capture register. 3. The capture operation is not performed if both the rising and falling edges are specified as the valid edge of TI000. 4. To ensure that the capture operation is performed properly, the capture trigger requires a pulse two cycles longer than the count clock selected by prescaler mode register 00 (PRM00). (3) 16-bit timer output control register 00 (TOC00) This register controls the operation of the 16-bit timer/event counter 00 output controller. It sets/resets the timer output F/F (LV00), enables/disables output inversion and 16-bit timer/event counter 00 timer output, enables/disables the one-shot pulse output operation, and sets the one-shot pulse output trigger via software. TOC00 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears TOC00 to 00H. User's Manual U15836EJ4V0UD 111 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-7. Format of 16-Bit Timer Output Control Register 00 (TOC00) Address: FFBDH Symbol TOC00 7 0 After reset: 00H <6> OSPT00 R/W <5> OSPE00 4 TOC004 <3> LVS00 <2> LVR00 1 TOC001 <0> TOE00 OSPT00 0 1 One-shot pulse output trigger control via software No one-shot pulse trigger One-shot pulse trigger OSPE00 0 1 One-shot pulse output operation control Successive pulse output mode One-shot pulse output mode Note TOC004 0 1 Timer output F/F control using match of CR010 and TM00 Disables inversion operation Enables inversion operation LVS00 0 0 1 1 LVR00 0 1 0 1 No change Timer output F/F status setting Timer output F/F reset (0) Timer output F/F set (1) Setting prohibited TOC001 0 1 Timer output F/F control using match of CR000 and TM00 Disables inversion operation Enables inversion operation TOE00 0 1 Timer output control Disables output (output fixed to level 0) Enables output Note The one-shot pulse output mode operates correctly only in the free-running mode and the mode in which clear & start occurs at the TI000 valid edge. In the mode in which clear & start occurs on a match between the TM00 register and CR000 register, one-shot pulse output is not possible because an overflow does not occur. Cautions 1. Timer operation must be stopped before setting other than TOC004. 2. LVS00 and LVR00 are 0 when they are read. 3. OSPT00 is automatically cleared after data is set, so 0 is read. 4. Do not set OSPT00 to 1 other than in one-shot pulse output mode. 5. A write interval of two cycles or more of the count clock selected by prescaler mode register 00 (PRM00) is required to write to OSPT00 successively. 6. Do not set LVS00 to 1 before TOE00, and do not set LVS00 and TOE00 to 1 simultaneously. 112 User's Manual U15836EJ4V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (4) Prescaler mode register 00 (PRM00) This register is used to set the 16-bit timer counter 00 (TM00) count clock and TI000 and TI010 input valid edges. PRM00 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears PRM00 to 00H. Figure 6-8. Format of Prescaler Mode Register 00 (PRM00) Address: FFBBH Symbol PRM00 7 ES101 After reset: 00H 6 ES100 R/W 5 ES001 4 ES000 3 0 2 0 1 PRM001 0 PRM000 ES101 0 0 1 1 ES100 0 1 0 1 Falling edge Rising edge Setting prohibited TI010 valid edge selection Both falling and rising edges ES001 0 0 1 1 ES000 0 1 0 1 Falling edge Rising edge Setting prohibited TI000 valid edge selection Both falling and rising edges PRM001 0 0 1 1 PRM000 0 1 0 1 fX (10 MHz) fX/2 (2.5 MHz) fX/2 (39.06 kHz) TI000 valid edge Note 8 2 Count clock selection Note The external clock requires a pulse two cycles longer than the internal clock (fX). Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the Ring-OSC oscillator is divided and supplied as the count clock. If the count clock is the Ring-OSC clock, the operation of 16-bit timer/event counter 00 is not guaranteed. When an external clock is used and when the Ring-OSC clock is selected and supplied to the CPU, the operation of 16-bit timer/event counter 00 is not guaranteed, either, because the Ring-OSC clock is supplied as the sampling clock to eliminate noise. 2. Always set data to PRM00 after stopping the timer operation. 3. If the valid edge of TI000 is to be set for the count clock, do not set the clear & start mode using the valid edge of TI000 and the capture trigger. 4. If the TI000 or TI010 pin is high level immediately after system reset, the rising edge is immediately detected after the rising edge or both the rising and falling edges are set as the valid edge(s) of the TI000 pin or TI010 pin to enable the operation of 16-bit timer counter 00 (TM00). Care is therefore required when pulling up the TI000 or TI010 pin. However, when reenabling operation after the operation has been stopped once, the rising edge is not detected. User's Manual U15836EJ4V0UD 113 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Caution 5. When P01 is used as the TI010 valid edge input pin, it cannot be used as the timer output (TO00), and when used as TO00, it cannot be used as the TI010 valid edge input pin. Remarks 1. fX: X1 input clock oscillation frequency 2. TI000, TI010: 16-bit timer/event counter 00 input pin 3. Figures in parentheses are for operation with fX = 10 MHz. (5) Port mode register 0 (PM0) This register sets port 0 input/output in 1-bit units. When using the P01/TO00/TI010 pin for timer output, set PM01 and the output latch of P01 to 0. Clear PM01 to 0 to when using the P01/TO00/TI010 pin as a timer input pin. The output latch of P01 at this time may be 0 or 1. PM0 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM0 to FFH. Figure 6-9. Format of Port Mode Register 0 (PM0) Address: FF20H Symbol PM0 7 1 6 1 After reset: FFH 5 1 4 1 R/W 3 2 1 0 PM03 PM02 PM01 PM00 PM0n 0 1 P0n pin I/O mode selection (n = 0 to 3) Output mode (output buffer on) Input mode (output buffer off) 114 User's Manual U15836EJ4V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4 Operation of 16-Bit Timer/Event Counter 00 6.4.1 Interval timer operation Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown in Figure 6-10 allows operation as an interval timer. Setting The basic operation setting procedure is as follows. <1> Set the CRC00 register (see Figure 6-10 for the set value). <2> Set any value to the CR000 register. <3> Set the count clock by using the PRM000 register. <4> Set the TMC00 register to start the operation (see Figure 6-10 for the set value). Caution CR000 cannot be rewritten during TM00 operation. Remark For how to enable the INTTM000 interrupt, see CHAPTER 14 INTERRUPT FUNCTIONS. Interrupt requests are generated repeatedly using the count value preset in 16-bit timer capture/compare register 000 (CR000) as the interval. When the count value of 16-bit timer counter 00 (TM00) matches the value set in CR000, counting continues with the TM00 value cleared to 0 and the interrupt request signal (INTTM000) is generated. The count clock of the 16-bit timer/event counter 00 can be selected with bits 0 and 1 (PRM000, PRM001) of prescaler mode register 00 (PRM00). User's Manual U15836EJ4V0UD 115 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-10. Control Register Settings for Interval Timer Operation (a) 16-bit timer mode control register 00 (TMC00) 7 TMC00 0 6 0 5 0 4 0 TMC003 TMC002 TMC001 OVF00 1 1 0/1 0 Clears and starts on match between TM00 and CR000. (b) Capture/compare control register 00 (CRC00) 7 CRC00 0 6 0 5 0 4 0 3 0 CRC002 CRC001 CRC000 0/1 0/1 0 CR000 used as compare register (c) Prescaler mode register 00 (PRM00) ES101 ES100 ES001 ES000 PRM00 0/1 0/1 0/1 0/1 3 0 2 0 PRM001 PRM000 0/1 0/1 Selects count clock. Setting invalid (setting "10" is prohibited.) Setting invalid (setting "10" is prohibited.) Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with the interval timer. See the description of the respective control registers for details. 116 User's Manual U15836EJ4V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-11. Interval Timer Configuration Diagram 16-bit timer capture/compare register 000 (CR000) INTTM000 fX fX/22 fX/28 TI000/P00 Noise eliminator Selector 16-bit timer counter 00 (TM00) OVF00 Note Clear circuit fX Note OVF00 is set to 1 only when CR000 is set to FFFFH. Figure 6-12. Timing of Interval Timer Operation t Count clock TM00 count value 0000H 0001H N 0000H 0001H Clear N N 0000H 0001H Clear N N N Timer operation enabled CR000 INTTM000 N Interrupt acknowledged Interrupt acknowledged Remark Interval time = (N + 1) x t N = 0001H to FFFFH User's Manual U15836EJ4V0UD 117 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.2 PPG output operations Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown in Figure 6-13 allows operation as PPG (Programmable Pulse Generator) output. Setting The basic operation setting procedure is as follows. <1> Set the CRC00 register (see Figure 6-13 for the set value). <2> Set any value to the CR000 register as the cycle. <3> Set any value to the CR010 register as the duty factor. <4> Set the TOC00 register (see Figure 6-13 for the set value). <5> Set the count clock by using the PRM00 register. <6> Set the TMC00 register to start the operation (see Figure 6-13 for the set value). Caution To change the value of the duty factor (the value of the CR010 register) during operation, see Caution 2 in Figure 6-15 PPG Output Operation Timing. Remarks 1. For the setting of the TO00 pin, see 6.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM000 interrupt, see CHAPTER 14 INTERRUPT FUNCTIONS. In the PPG output operation, rectangular waves are output from the TO00 pin with the pulse width and the cycle that correspond to the count values preset in 16-bit timer capture/compare register 010 (CR010) and in 16-bit timer capture/compare register 000 (CR000), respectively. 118 User's Manual U15836EJ4V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-13. Control Register Settings for PPG Output Operation (a) 16-bit timer mode control register 00 (TMC00) 7 TMC00 0 6 0 5 0 4 0 TMC003 TMC002 TMC001 OVF00 1 1 0 0 Clears and starts on match between TM00 and CR000. (b) Capture/compare control register 00 (CRC00) 7 CRC00 0 6 0 5 0 4 0 3 0 CRC002 CRC001 CRC000 0 x 0 CR000 used as compare register CR010 used as compare register (c) 16-bit timer output control register 00 (TOC00) 7 TOC00 0 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 0 0 1 0/1 0/1 1 1 Enables TO00 output Inverts output on match between TM00 and CR000 Specifies initial value of TO00 output F/F (setting "11" is prohibited.) Inverts output on match between TM00 and CR010 Disables one-shot pulse output (d) Prescaler mode register 00 (PRM00) ES101 ES100 ES001 ES000 PRM00 0/1 0/1 0/1 0/1 3 0 2 0 PRM001 PRM000 0/1 0/1 Selects count clock. Setting invalid (setting "10" is prohibited.) Setting invalid (setting "10" is prohibited.) Cautions 1. Values in the following range should be set in CR000 and CR010: 0000H CR010 < CR000 FFFFH 2. The cycle of the pulse generated through PPG output (CR000 setting value + 1) has a duty of (CR010 setting value + 1)/(CR000 setting value + 1). Remark x: Don't care User's Manual U15836EJ4V0UD 119 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-14. Configuration of PPG Output 16-bit timer capture/compare register 000 (CR000) fX fX/22 fX/28 TI000/P00 Noise eliminator fX Selector 16-bit timer counter 00 (TM00) Clear circuit Output controller TO00/TI010/P01 16-bit timer capture/compare register 010 (CR010) Figure 6-15. PPG Output Operation Timing t Count clock TM00 count value N 0000H 0001H M-1 M N-1 N 0000H 0001H Clear CR000 capture value CR010 capture value TO00 Pulse width: (M + 1) x t 1 cycle: (N + 1) x t N M Clear Cautions 1. CR000 cannot be rewritten during TM00 operation. 2. In the PPG output operation, change the pulse width (rewrite CR010) during TM00 operation using the following procedure. <1> <2> <3> <4> <5> <6> <7> Remark Disable the timer output inversion operation by match of TM00 and CR010 (TOC004 = 0) Disable the INTTM010 interrupt (TMMK010 = 1) Rewrite CR010 Wait for 1 cycle of the TM00 count clock Enable the timer output inversion operation by match of TM00 and CR010 (TOC004 = 1) Clear the interrupt request flag of INTTM010 (TMIF010 = 0) Enable the INTTM010 interrupt (TMMK010 = 0) 0000H M < N FFFFH 120 User's Manual U15836EJ4V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.3 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI000 pin and TI010 pin using 16-bit timer counter 00 (TM00). There are two measurement methods: measuring with TM00 used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the TI000 pin. When an interrupt occurs, read the valid value of the capture register, check the overflow flag, and then calculate the necessary pulse width. Clear the overflow flag after checking it. The capture operation is not performed until the signal pulse width is sampled in the count clock cycle selected by prescaler mode register 00 (PRM00) and the valid level of the TI000 or TI010 pin is detected twice, thus eliminating noise with a short pulse width. Figure 6-16. CR010 Capture Operation with Rising Edge Specified Count clock TM00 TI000 Rising edge detection CR010 INTTM010 N N-3 N-2 N-1 N N+1 Setting The basic operation setting procedure is as follows. <1> Set the CRC00 register (see Figures 6-17, 6-20, 6-22, and 6-24 for the set value). <2> Set the count clock by using the PRM00 register. <3> Set the TMC00 register to start the operation (see Figures 6-17, 6-20, 6-22, and 6-24 for the set value). Caution To use two capture registers, set the TI000 and TI010 pins. Remarks 1. For the setting of the TI000 (or TI010) pin, see 6.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM000 (or INTTM010) interrupt, see CHAPTER 14 FUNCTIONS. INTERRUPT User's Manual U15836EJ4V0UD 121 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (1) Pulse width measurement with free-running counter and one capture register When 16-bit timer counter 00 (TM00) is operated in free-running mode, and the edge specified by prescaler mode register 00 (PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and an external interrupt request signal (INTTM010) is set. Specify both the rising and falling edges by using bits 4 and 5 (ES000 and ES001) of PRM00. Sampling is performed using the count clock selected by PRM00, and a capture operation is only performed when the valid level of the TI000 pin is detected twice, thus eliminating noise with a short pulse width. Figure 6-17. Control Register Settings for Pulse Width Measurement with Free-Running Counter and One Capture Register (When TI000 and CR010 Are Used) (a) 16-bit timer mode control register 00 (TMC00) 7 TMC00 0 6 0 5 0 4 0 TMC003 TMC002 TMC001 OVF00 0 1 0/1 0 Free-running mode (b) Capture/compare control register 00 (CRC00) 7 CRC00 0 6 0 5 0 4 0 3 0 CRC002 CRC001 CRC000 1 0/1 0 CR000 used as compare register CR010 used as capture register (c) Prescaler mode register 00 (PRM00) ES101 ES100 ES001 ES000 PRM00 0/1 0/1 1 1 3 0 2 0 PRM001 PRM000 0/1 0/1 Selects count clock (setting "11" is prohibited). Specifies both edges for pulse width detection. Setting invalid (setting "10" is prohibited.) Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. See the description of the respective control registers for details. 122 User's Manual U15836EJ4V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-18. Configuration Diagram for Pulse Width Measurement with Free-Running Counter fX Selector fX/22 fX/28 16-bit timer counter 00 (TM00) OVF00 TI000 16-bit timer capture/compare register 010 (CR010) INTTM010 Internal bus Figure 6-19. Timing of Pulse Width Measurement Operation with Free-Running Counter and One Capture Register (with Both Edges Specified) t Count clock TM00 count value TI000 pin input CR010 capture value INTTM010 OVF00 (D1 - D0) x t (10000H - D1 + D2) x t Note (D3 - D2) x t D0 D1 D2 D3 0000H 0001H D0 D0 + 1 D1 D1 + 1 FFFFH 0000H D2 D3 Note Clear OVF00 by software. User's Manual U15836EJ4V0UD 123 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (2) Measurement of two pulse widths with free-running counter When 16-bit timer counter 00 (TM00) is operated in free-running mode, it is possible to simultaneously measure the pulse widths of the two signals input to the TI000 pin and the TI010 pin. When the edge specified by bits 4 and 5 (ES000 and ES001) of prescaler mode register 00 (PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and an interrupt request signal (INTTM010) is set. Also, when the edge specified by bits 6 and 7 (ES100 and ES101) of PRM00 is input to the TI010 pin, the value of TM00 is taken into 16-bit timer capture/compare register 000 (CR000) and an interrupt request signal (INTTM000) is set. Specify both the rising and falling edges as the edges of the TI000 and TI010 pins, by using bits 4 and 5 (ES000 and ES001) and bits 6 and 7 (ES100 and ES101) of PRM00. Sampling is performed at the interval selected by prescaler mode register 00 (PRM00), and a capture operation is only performed when the valid level of the TI000 pin or TI010 pin is detected twice, thus eliminating noise with a short pulse width. Figure 6-20. Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter (a) 16-bit timer mode control register 00 (TMC00) 7 TMC00 0 6 0 5 0 4 0 TMC003 TMC002 TMC001 OVF00 0 1 0/1 0 Free-running mode (b) Capture/compare control register 00 (CRC00) 7 CRC00 0 6 0 5 0 4 0 3 0 CRC002 CRC001 CRC000 1 0 1 CR000 used as capture register Captures valid edge of TI010 pin to CR000 CR010 used as capture register (c) Prescaler mode register 00 (PRM00) ES101 ES100 ES001 ES000 PRM00 1 1 1 1 3 0 2 0 PRM001 PRM000 0/1 0/1 Selects count clock (setting "11" is prohibited). Specifies both edges for pulse width detection. Specifies both edges for pulse width detection. Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. See the description of the respective control registers for details. 124 User's Manual U15836EJ4V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-21. Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified) t Count clock TM00 count value TI000 pin input CR010 capture value INTTM010 TI010 pin input CR000 capture value INTTM000 OVF00 Note D1 D2 + 1 D0 D1 D2 0000H 0001H D0 D0 + 1 D1 D1 + 1 FFFFH 0000H D2 D2 + 1 D2 + 2 D3 (D1 - D0) x t (10000H - D1 + D2) x t (D3 - D2) x t (10000H - D1 + (D2 + 1)) x t Note Clear OVF00 by software. User's Manual U15836EJ4V0UD 125 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) Pulse width measurement with free-running counter and two capture registers When 16-bit timer counter 00 (TM00) is operated in free-running mode, it is possible to measure the pulse width of the signal input to the TI000 pin. When the rising or falling edge specified by bits 4 and 5 (ES000 and ES001) of prescaler mode register 00 (PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and an interrupt request signal (INTTM010) is set. Also, when the inverse edge to that of the capture operation is input into CR010, the value of TM00 is taken into 16-bit timer capture/compare register 000 (CR000). Sampling is performed at the interval selected by prescaler mode register 00 (PRM00), and a capture operation is only performed when the valid level of the TI000 pin is detected twice, thus eliminating noise with a short pulse width. Figure 6-22. Control Register Settings for Pulse Width Measurement with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) (a) 16-bit timer mode control register 00 (TMC00) 7 TMC00 0 6 0 5 0 4 0 TMC003 TMC002 TMC001 OVF00 0 1 0/1 0 Free-running mode (b) Capture/compare control register 00 (CRC00) 7 CRC00 0 6 0 5 0 4 0 3 0 CRC002 CRC001 CRC000 1 1 1 CR000 used as capture register Captures to CR000 at inverse edge to valid edge of TI000. CR010 used as capture register (c) Prescaler mode register 00 (PRM00) ES101 ES100 ES001 ES000 PRM00 0/1 0/1 0 1 3 0 2 0 PRM001 PRM000 0/1 0/1 Selects count clock (setting "11" is prohibited). Specifies rising edge for pulse width detection. Setting invalid (setting "10" is prohibited.) Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. See the description of the respective control registers for details. 126 User's Manual U15836EJ4V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-23. Timing of Pulse Width Measurement Operation with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) t Count clock TM00 count value TI000 pin input CR010 capture value CR000 capture value INTTM010 OVF00 (D1 - D0) x t (10000H - D1 + D2) x t Note (D3 - D2) x t D0 D1 D2 D3 0000H 0001H D0 D0 + 1 D1 D1 + 1 FFFFH 0000H D2 D2 + 1 D3 Note Clear OVF00 by software. (4) Pulse width measurement by means of restart When input of a valid edge to the TI000 pin is detected, the count value of 16-bit timer counter 00 (TM00) is taken into 16-bit timer capture/compare register 010 (CR010), and then the pulse width of the signal input to the TI000 pin is measured by clearing TM00 and restarting the count operation. Either of two edgesrising or fallingcan be selected using bits 4 and 5 (ES000 and ES001) of prescaler mode register 00 (PRM00). Sampling is performed using the count clock cycle selected by prescaler mode register 00 (PRM00) and a capture operation is only performed when the valid level of the TI000 pin is detected twice, thus eliminating noise with a short pulse width. User's Manual U15836EJ4V0UD 127 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-24. Control Register Settings for Pulse Width Measurement by Means of Restart (with Rising Edge Specified) (a) 16-bit timer mode control register 00 (TMC00) 7 TMC00 0 6 0 5 0 4 0 TMC003 TMC002 TMC001 OVF00 1 0 0/1 0 Clears and starts at valid edge of TI000 pin. (b) Capture/compare control register 00 (CRC00) 7 CRC00 0 6 0 5 0 4 0 3 0 CRC002 CRC001 CRC000 1 1 1 CR000 used as capture register Captures to CR000 at inverse edge to valid edge of TI000. CR010 used as capture register (c) Prescaler mode register 00 (PRM00) ES101 ES100 ES001 ES000 PRM00 0/1 0/1 0 1 3 0 2 0 PRM001 PRM000 0/1 0/1 Selects count clock (setting "11" is prohibited). Specifies rising edge for pulse width detection. Setting invalid (setting "10" is prohibited.) Figure 6-25. Timing of Pulse Width Measurement Operation by Means of Restart (with Rising Edge Specified) t Count clock TM00 count value TI000 pin input CR010 capture value CR000 capture value INTTM010 D1 x t D2 x t D0 D1 D2 0000H 0001H D0 0000H 0001H D1 D2 0000H 0001H 128 User's Manual U15836EJ4V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.4 External event counter operation Setting The basic operation setting procedure is as follows. <1> Set the CRC00 register (see Figure 6-26 for the set value). <2> Set the count clock by using the PRM00 register. <3> Set any value to the CR000 register (0000H cannot be set). <4> Set the TMC00 register to start the operation (see Figure 6-26 for the set value). Remarks 1. For the setting of the TI000 pin, see 6.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM000 interrupt, see CHAPTER 14 INTERRUPT FUNCTIONS. The external event counter counts the number of external clock pulses input to the TI000 pin using 16-bit timer counter 00 (TM00). TM00 is incremented each time the valid edge specified by prescaler mode register 00 (PRM00) is input. When the TM00 count value matches the 16-bit timer capture/compare register 000 (CR000) value, TM00 is cleared to 0 and the interrupt request signal (INTTM000) is generated. Input a value other than 0000H to CR000 (a count operation with 1-bit pulse cannot be carried out). Any of three edgesrising, falling, or both edgescan be selected using bits 4 and 5 (ES000 and ES001) of prescaler mode register 00 (PRM00). Sampling is performed using the internal clock (fX) and an operation is only performed when the valid level of the TI000 pin is detected twice, thus eliminating noise with a short pulse width. User's Manual U15836EJ4V0UD 129 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-26. Control Register Settings in External Event Counter Mode (with Rising Edge Specified) (a) 16-bit timer mode control register 00 (TMC00) 7 TMC00 0 6 0 5 0 4 0 TMC003 TMC002 TMC001 OVF00 1 1 0/1 0 Clears and starts on match between TM00 and CR000. (b) Capture/compare control register 00 (CRC00) 7 CRC00 0 6 0 5 0 4 0 3 0 CRC002 CRC001 CRC000 0/1 0/1 0 CR000 used as compare register (c) Prescaler mode register 00 (PRM00) ES101 ES100 ES001 ES000 PRM00 0/1 0/1 0 1 3 0 2 0 PRM001 PRM000 1 1 Selects external clock. Specifies rising edge for pulse width detection. Setting invalid (setting "10" is prohibited.) Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with the external event counter. See the description of the respective control registers for details. 130 User's Manual U15836EJ4V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-27. Configuration Diagram of External Event Counter Internal bus 16-bit timer capture/compare register 000 (CR000) Match INTTM000 Clear fX Noise eliminator 16-bit timer counter 00 (TM00) OVF00Note Valid edge of TI000 Note OVF00 is set to 1 only when CR000 is set to FFFFH. Figure 6-28. External Event Counter Operation Timing (with Rising Edge Specified) TI000 pin input TM00 count value CR000 INTTM000 0000H 0001H 0002H 0003H 0004H 0005H N N-1 N 0000H 0001H 0002H 0003H Caution When reading the external event counter count value, TM00 should be read. User's Manual U15836EJ4V0UD 131 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.5 Square-wave output operation Setting The basic operation setting procedure is as follows. <1> Set the count clock by using the PRM00 register. <2> Set the CRC00 register (see Figure 6-29 for the set value). <3> Set the TOC00 register (see Figure 6-29 for the set value). <4> Set any value to the CR000 register (0000H cannot be set). <5> Set the TMC00 register to start the operation (see Figure 6-29 for the set value). Caution CR000 cannot be rewritten during TM00 operation. Remarks 1. For the setting of the TO00 pin, see 6.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM000 interrupt, see CHAPTER 14 INTERRUPT FUNCTIONS. A square wave with any selected frequency can be output at intervals determined by the count value preset to 16bit timer capture/compare register 000 (CR000). The TO00 pin output status is reversed at intervals determined by the count value preset to CR000 +1 by setting bit 0 (TOE00) and bit 1 (TOC001) of 16-bit timer output control register 00 (TOC00) to 1. This enables a square wave with any selected frequency to be output. Figure 6-29. Control Register Settings in Square-Wave Output Mode (1/2) (a) 16-bit timer mode control register 00 (TMC00) 7 TMC00 0 6 0 5 0 4 0 TMC003 TMC002 TMC001 OVF00 1 1 0 0 Clears and starts on match between TM00 and CR000. (b) Capture/compare control register 00 (CRC00) 7 CRC00 0 6 0 5 0 4 0 3 0 CRC002 CRC001 CRC000 0/1 0/1 0 CR000 used as compare register 132 User's Manual U15836EJ4V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-29. Control Register Settings in Square-Wave Output Mode (2/2) (c) 16-bit timer output control register 00 (TOC00) 7 TOC00 0 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 0 0 0 0/1 0/1 1 1 Enables TO00 output. Inverts output on match between TM00 and CR000. Specifies initial value of TO00 output F/F (setting "11" is prohibited). Does not invert output on match between TM00 and CR010. Disables one-shot pulse output. (d) Prescaler mode register 00 (PRM00) ES101 ES100 ES001 ES000 PRM00 0/1 0/1 0/1 0/1 3 0 2 0 PRM001 PRM000 0/1 0/1 Selects count clock. Setting invalid (setting "10" is prohibited.) Setting invalid (setting "10" is prohibited.) Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with square-wave output. See the description of the respective control registers for details. Figure 6-30. Square-Wave Output Operation Timing Count clock TM00 count value CR000 INTTM000 TO00 pin output 0000H 0001H 0002H N N-1 N 0000H 0001H 0002H N-1 N 0000H User's Manual U15836EJ4V0UD 133 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.6 One-shot pulse output operation 16-bit timer/event counter 00 can output a one-shot pulse in synchronization with a software trigger or an external trigger (TI000 pin input). Setting The basic operation setting procedure is as follows. <1> Set the count clock by using the PRM00 register. <2> Set the CRC00 register (see Figures 6-31 and 6-33 for the set value). <3> Set the TOC00 register (see Figures 6-31 and 6-33 for the set value). <4> Set any value to the CR000 and CR010 registers (0000H cannot be set). <5> Set the TMC00 register to start the operation (see Figures 6-31 and 6-33 for the set value). Remarks 1. For the setting of the TO00 pin, see 6.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM000 (if necessary, INTTM010) interrupt, see CHAPTER 14 INTERRUPT FUNCTIONS. (1) One-shot pulse output with software trigger A one-shot pulse can be output from the TO00 pin by setting 16-bit timer mode control register 00 (TMC00), capture/compare control register 00 (CRC00), and 16-bit timer output control register 00 (TOC00) as shown in Figure 6-31, and by setting bit 6 (OSPT00) of the TOC00 register to 1 by software. By setting the OSPT00 bit to 1, 16-bit timer/event counter 00 is cleared and started, and its output becomes active at the count value (N) set in advance to 16-bit timer capture/compare register 010 (CR010). After that, the output becomes inactive at the count value (M) set in advance to 16-bit timer capture/compare register 000 (CR000)Note. Even after the one-shot pulse has been output, the TM00 register continues its operation. To stop the TM00 register, the TMC003 and TMC002 bits of the TMC00 register must be set to 00. Note The case where N < M is described here. When N > M, the output becomes active with the CR000 register and inactive with the CR010 register. Do not set N to M. Cautions 1. Do not set the OSPT00 bit to 1 while the one-shot pulse is being output. To output the oneshot pulse again, wait until the current one-shot pulse output is completed. 2. When using the one-shot pulse output of 16-bit timer/event counter 00 with a software trigger, do not change the level of the TI000 pin or its alternate-function port pin. Because the external trigger is valid even in this case, the timer is cleared and started even at the level of the TI000 pin or its alternate-function port pin, resulting in the output of a pulse at an undesired timing. 134 User's Manual U15836EJ4V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-31. Control Register Settings for One-Shot Pulse Output with Software Trigger (a) 16-bit timer mode control register 00 (TMC00) 7 TMC00 0 6 0 5 0 4 0 TMC003 0 TMC002 TMC001 1 0 OVF00 0 Free-running mode (b) Capture/compare control register 00 (CRC00) 7 CRC00 0 6 0 5 0 4 0 3 0 CRC002 CRC001 CRC000 0 0/1 0 CR000 as compare register CR010 as compare register (c) 16-bit timer output control register 00 (TOC00) 7 TOC00 0 OSPT00 OSPE00 TOC004 0 1 1 LVS00 0/1 LVR00 0/1 TOC001 1 TOE00 1 Enables TO00 output Inverts output upon match between TM00 and CR000 Specifies initial value of TO00 output F/F (setting "11" is prohibited.) Inverts output upon match between TM00 and CR010 Sets one-shot pulse output mode Set to 1 for output (d) Prescaler mode register 00 (PRM00) ES101 PRM00 0/1 ES100 0/1 ES001 0/1 ES000 0/1 3 2 PRM001 PRM000 0/1 0/1 0 0 Selects count clock. Setting invalid (setting "10" is prohibited.) Setting invalid (setting "10" is prohibited.) Caution Do not set 0000H to the CR000 and CR010 registers. User's Manual U15836EJ4V0UD 135 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-32. Timing of One-Shot Pulse Output Operation with Software Trigger Set TMC00 to 0CH (TM00 count starts) Count clock TM00 count 0000H 0001H CR010 set value CR000 set value OSPT00 INTTM010 INTTM000 TO00 pin output N M N N+1 N M 0000H N-1 N N M M-1 M M+1 M+2 N M Caution 16-bit timer counter 00 starts operating as soon as the TMC003 and TMC002 bits are set to a value other than 00 (operation stop mode). Remark N 136 User's Manual U15836EJ4V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-33. Control Register Settings for One-Shot Pulse Output with External Trigger (with Rising Edge Specified) (a) 16-bit timer mode control register 00 (TMC00) 7 TMC00 0 6 0 5 0 4 0 TMC003 1 TMC002 TMC001 0 0 OVF00 0 Clears and starts at valid edge of TI000 pin (b) Capture/compare control register 00 (CRC00) 7 CRC00 0 6 0 5 0 4 0 3 0 CRC002 CRC001 0 0/1 CRC000 0 CR000 used as compare register CR010 used as compare register (c) 16-bit timer output control register 00 (TOC00) 7 TOC00 0 OSPT00 OSPE00 TOC004 0 1 1 LVS00 0/1 LVR00 0/1 TOC001 1 TOE00 1 Enables TO00 output Inverts output upon match between TM00 and CR000 Specifies initial value of TO00 output F/F (setting "11" is prohibited.) Inverts output upon match between TM00 and CR010 Sets one-shot pulse output mode (d) Prescaler mode register 00 (PRM00) ES101 PRM00 0/1 ES100 0/1 ES001 0 ES000 1 3 0 2 0 PRM001 PRM000 0/1 0/1 Selects count clock (setting "11" is prohibited). Specifies the rising edge for pulse width detection. Setting invalid (setting "10" is prohibited.) Caution Do not set the CR000 and CR010 registers to 0000H. User's Manual U15836EJ4V0UD 137 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-34. Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified) When TMC00 is set to 08H (TM00 count starts) t Count clock TM00 count value 0000H 0001H CR010 set value CR000 set value TI000 pin input INTTM010 INTTM000 TO00 pin output N M 0000H N M N N+1 N+2 N M M-2 M-1 M N M M+1 M+2 Caution 16-bit timer counter 00 starts operating as soon as the TMC002 and TMC003 bits are set to a value other than 00 (operation stop mode). Remark N User's Manual U15836EJ4V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.5 Cautions for 16-Bit Timer/Event Counter 00 (1) Timer start errors An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 16-bit timer counter 00 (TM00) is started asynchronously to the count clock. Figure 6-35. Start Timing of 16-Bit Timer Counter 00 (TM00) Count clock TM00 count value 0000H 0001H 0002H 0003H 0004H Timer start (2) 16-bit timer capture/compare register setting (in the mode in which clear & start occurs on match between TM00 and CR000) Set 16-bit timer capture/compare registers 000, 010 (CR000, CR010) to other than 0000H. This means a 1-pulse count operation cannot be performed when 16-bit timer/event counter 00 is used as an event counter. (3) Capture register data retention timing The values of 16-bit timer capture/compare registers 000 and 010 (CR000 and CR010) are not guaranteed after 16-bit timer/event counter 00 has been stopped. (4) Valid edge setting Set the valid edge of the TI000 pin after setting bits 2 and 3 (TMC002 and TMC003) of 16-bit timer mode control register 00 (TMC00) to 0, 0, respectively, and then stopping timer operation. The valid edge is set using bits 4 and 5 (ES000 and ES001) of prescaler mode register 00 (PRM00). (5) Re-triggering one-shot pulse (a) One-shot pulse output by software When a one-shot pulse is output, do not set the OSPT00 bit to 1. Do not output the one-shot pulse again until INTTM000, which occurs upon a match with the CR000 register, or INTTM010, which occurs upon a match with the CR010 register, occurs. (b) One-shot pulse output with external trigger If the external trigger occurs again while a one-shot pulse is output, it is ignored. (c) One-shot pulse output function When using the one-shot pulse output of 16-bit timer/event counter 00 with a software trigger, do not change the level of the TI000 pin or its alternate function port pin. Because the external trigger is valid even in this case, the timer is cleared and started even at the level of the TI000 pin or its alternate function port pin, resulting in the output of a pulse at an undesired timing. User's Manual U15836EJ4V0UD 139 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (6) Operation of OVF00 flag <1> The OVF00 flag is also set to 1 in the following case. When of the following modes: the mode in which clear & start occurs on a match between TM00 and CR000, the mode in which clear & start occurs on a TI00 valid edge, or the free-running mode, is selected CR000 is set to FFFFH TM00 is counted up from FFFFH to 0000H. Figure 6-36. Operation Timing of OVF00 Flag Count clock CR000 TM00 OVF00 INTTM000 FFFFH FFFEH FFFFH 0000H 0001H <2> Even if the OVF00 flag is cleared before the next count clock (before TM00 becomes 0001H) after the occurrence of TM00 overflow, the OVF00 flag is re-set newly and clear is disabled. (7) Conflicting operations Conflict between the read period of the 16-bit timer capture/compare register (CR000/CR010) and capture trigger input (CR000/CR010 used as capture register) Capture trigger input has priority. The data read from CR000/CR010 is undefined. Figure 6-37. Capture Register Data Retention Timing Count clock TM00 count value Edge input INTTM010 Capture read signal CR010 capture value X N+2 M+1 N N+1 N+2 M M+1 M+2 Capture Capture, but read value is not guaranteed 140 User's Manual U15836EJ4V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (8) Timer operation <1> Even if 16-bit timer counter 00 (TM00) is read, the value is not captured by 16-bit timer capture/compare register 010 (CR010). <2> Regardless of the CPU's operation mode, when the timer stops, the input signals to the TI000/TI010 pins are not acknowledged. <3> The one-shot pulse output mode operates correctly only in the free-running mode and the mode in which clear & start occurs at the TI000 valid edge. In the mode in which clear & start occurs on a match between the TM00 register and CR000 register, one-shot pulse output is not possible because an overflow does not occur. (9) Capture operation <1> If TI000 valid edge is specified as the count clock, a capture operation by the capture register specified as the trigger for TI000 is not possible. <2> To ensure the reliability of the capture operation, the capture trigger requires a pulse two cycles longer than the count clock selected by prescaler mode register 00 (PRM00). <3> The capture operation is performed at the falling edge of the count clock. An interrupt request input (INTTM000/INTTM010), however, is generated at the rise of the next count clock. (10) Compare operation A capture operation may not be performed for CR000/CR010 set in compare mode even if a capture trigger has been input. (11) Edge detection <1> If the TI000 or TI010 pin is high level immediately after system reset and the rising edge or both the rising and falling edges are specified as the valid edge of the TI000 or TI010 pin to enable the 16-bit timer counter 00 (TM00) operation, a rising edge is detected immediately after the operation is enabled. Be careful therefore when pulling up the TI000 or TI010 pin. However, the rising edge is not detected at restart after the operation has been stopped once. <2> The sampling clock used to eliminate noise differs when the TI000 valid edge is used as the count clock and when it is used as a capture trigger. In the former case, the count clock is fX, and in the latter case the count clock is selected by prescaler mode register 00 (PRM00). The capture operation is started only after a valid level is detected twice by sampling the valid edge, thus eliminating noise with a short pulse width. User's Manual U15836EJ4V0UD 141 CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50 7.1 Functions of 8-Bit Timer/Event Counter 50 8-bit timer/event counter 50 has the following functions. * Interval timer * External event counter * Square-wave output * PWM output Figure 7-1 shows the block diagram of 8-bit timer/event counter 50. Figure 7-1. Block Diagram of 8-Bit Timer/Event Counter 50 Internal bus Mask circuit 8-bit timer compare register 50 (CR50) TI50/TO50/P17 fX fX/2 fX/22 fX/26 fX/28 fX/213 Match Selector Selector Note 1 INTTM50 To TMH0 To UART0 To UART6 TO50/ TI50/P17 Output latch (P17) PM17 8-bit timer OVF counter 50 (TM50) Clear R Note 2 S R Invert level 3 Selector TCL502 TCL501 TCL500 Timer clock selection register 50 (TCL50) TCE50 TMC506 LVS50 LVR50 TMC501 TOE50 8-bit timer mode control register 50 (TMC50) Internal bus Notes 1. 2. Timer output F/F PWM output F/F 142 User's Manual U15836EJ4V0UD Selector S Q INV CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50 7.2 Configuration of 8-Bit Timer/Event Counter 50 8-bit timer/event counter 50 includes the following hardware. Table 7-1. Configuration of 8-Bit Timer/Event Counter 50 Item Timer register Register Timer input Timer output Control registers Configuration 8-bit timer counter 50 (TM50) 8-bit timer compare register 50 (CR50) TI50 TO50 Timer clock selection register 50 (TCL50) 8-bit timer mode control register 50 (TMC50) Port mode register 1 (PM1) Port register 1 (P1) (1) 8-bit timer counter 50 (TM50) TM50 is an 8-bit register that counts the count pulses and is read-only. The counter is incremented is synchronization with the rising edge of the count clock. Figure 7-2. Format of 8-Bit Timer Counter 50 (TM50) Address: FF16H Symbol TM50 After reset: 00H R In the following situations, the count value is cleared to 00H. <1> RESET input <2> When TCE50 is cleared <3> When TM50 and CR50 match in clear & start mode if this mode was entered upon a match of TM50 and CR50 values. User's Manual U15836EJ4V0UD 143 CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50 (2) 8-bit timer compare register 50 (CR50) CR50 can be read and written by an 8-bit memory manipulation instruction. Except in PWM mode, the value set in CR50 is constantly compared with the 8-bit timer counter 50 (TM50) count value, and an interrupt request (INTTM50) is generated if they match. In PWM mode, when the TO50 pin becomes high level due to a TM50 overflow and the values of TM50 and CR50 match, the TO50 pin becomes inactive. The value of CR50 can be set within 00H to FFH. RESET input clears this register to 00H. Figure 7-3. Format of 8-Bit Timer Compare Register 50 (CR50) Address: FF17H Symbol CR50 After reset: 00H R/W Cautions 1. In the clear & start mode entered on a match of TM50 and CR50 (TMC506 = 0), do not write other values to CR50 during operation. 2. In PWM mode, make the CR50 rewrite period 3 count clocks of the count clock (clock selected by TCL50) or more. 144 User's Manual U15836EJ4V0UD CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50 7.3 Registers Controlling 8-Bit Timer/Event Counter 50 The following four registers are used to control 8-bit timer/event counter 50. * Timer four selection register 50 (TCL50) * 8-bit timer mode control register 50 (TMC50) * Port mode register 1 (PM1) * Port register 1 (P1) (1) Timer clock selection register 50 (TCL50) This register sets the count clock of 8-bit timer/event counter 50 and the valid edge of TI50 input. TCL50 can be set by an 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 7-4. Format of Timer Clock Selection Register 50 (TCL50) Address: FF6AH Symbol TCL50 7 0 After reset: 00H 6 0 R/W 5 0 4 0 3 0 2 TCL502 1 TCL501 0 TCL500 TCL502 0 0 0 0 1 1 1 1 TCL501 0 0 1 1 0 0 1 1 TCL500 0 1 0 1 0 1 0 1 TI50 falling edge TI50 rising edge fX (10 MHz) fX/2 (5 MHz) fX/2 (2.5 MHz) fX/2 (156.25 kHz) fX/2 (39.06 kHz) fX/2 (1.22 kHz) 13 8 6 2 Count clock selection Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the Ring-OSC oscillator is divided and supplied as the count clock. If the count clock is the Ring-OSC clock, the operation of 8-bit timer/event counter 50 is not guaranteed. 2. When rewriting TCL50 to other than the same data, stop the timer operation beforehand. 3. Be sure to set bits 3 to 7 to 0. Remarks 1. fX: X1 input clock oscillation frequency 2. Figures in parentheses apply to operation at fX = 10 MHz. User's Manual U15836EJ4V0UD 145 CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50 (2) 8-bit timer mode control register 50 (TMC50) TMC50 is a register that performs the following five types of settings. <1> 8-bit timer counter 50 (TM50) count operation control <2> 8-bit timer counter 50 (TM50) operating mode selection <3> Timer output F/F (flip-flop) status setting <4> Active level selection in timer F/F control or PWM (free-running) mode <5> Timer output control TMC50 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 7-5 shows the TMC50 format. Figure 7-5. Format of 8-Bit Timer Mode Control Register 50 (TMC50) Address: FF6BH Symbol TMC50 After reset: 00H <7> TCE50 6 TMC506 R/W 5 0 4 0 <3> LVS50 <2> LVR50 1 TMC501 <0> TOE50 TCE50 0 1 TM50 count operation control After clearing to 0, count operation disabled (counter stopped) Count operation start TMC506 0 1 TM50 operating mode selection Clear & start mode by match between TM50 and CR50 PWM (free-running) mode LVS50 0 0 1 1 LVR50 0 1 0 1 No change Timer output F/F status setting Timer output F/F reset (0) Timer output F/F set (1) Setting prohibited TMC501 In other modes (TMC506 = 0) Timer F/F control In PWM mode (TMC506 = 1) Active level selection Active high Active low 0 1 Inversion operation disabled Inversion operation enabled TOE50 0 1 Timer output control Output disabled (TM50 outputs the low level) Output enabled 146 User's Manual U15836EJ4V0UD CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50 Cautions 1. The settings of LVS50 and LVR50 are valid in other than PWM mode. 2. Do not rewrite following bits simultaneously. * TMC501 and TOE50 * TMC506 and TOE50 * TMC501 and TMC506 * TMC506 and LVS50, LVR50 * TOE50 and LVS50, LVR50 3. Stop operation before rewriting TMC506. Remarks 1. In PWM mode, PWM output is made inactive by setting TCE50 to 0. 2. If LVS50 and LVR50 are read, 0 is read. 3. The values of the TMC506, LVS50, LVR50, TMC501, and TOE50 bits are reflected at the TO50 pin regardless of the value of TCE50. (3) Port mode register 1 (PM1) This register sets port 1 input/output in 1-bit units. When using the P17/TO50/TI50 pin for timer output, set PM17 and the output latches of P17 to 0. Set PM17 to 1 when using the P17/TO50/TI50 pin as a timer input pin. The output latch of P17 at this time may be 0 or 1. PM1 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to FFH. Figure 7-6. Format of Port Mode Register 1 (PM1) Address: FF21H Symbol PM1 7 PM17 After reset: FFH 6 PM16 R/W 5 PM15 4 PM14 3 PM13 2 PM12 1 PM11 0 PM10 PM1n 0 1 P1n pin I/O mode selection (n = 0 to 7) Output mode (output buffer on) Input mode (output buffer off) User's Manual U15836EJ4V0UD 147 CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50 7.4 Operations of 8-Bit Timer/Event Counter 50 7.4.1 Operation as interval timer 8-bit timer/event counter 50 operates as an interval timer that generates interrupt requests repeatedly at intervals of the count value preset to 8-bit timer compare register 50 (CR50). When the count value of 8-bit timer counter 50 (TM50) matches the value set to CR50, counting continues with the TM50 value cleared to 0 and an interrupt request signal (INTTM50) is generated. The count clock of TM50 can be selected with bits 0 to 2 (TCL500 to TCL502) of timer clock selection register 50 (TCL50). Setting <1> Set the registers. * TCL50: * CR50: * TMC50: Select the count clock. Compare value Stop the count operation, select clear & start mode entered on a match of TM50 and CR50. (TMC50 = 0000xxx0B x = Don't care) <2> After TCE50 = 1 is set, the count operation starts. <3> If the values of TM50 and CR50 match, INTTM50 is generated (TM50 is cleared to 00H). <4> INTTM50 is generated repeatedly at the same interval. Set TCE50 to 0 to stop the count operation. Caution Do not write other values to CR50 during operation. Figure 7-7. Interval Timer Operation Timing (1/2) (a) Basic operation t Count clock TM50 count value 00H 01H N 00H 01H N 00H 01H N Count start CR50 TCE50 INTTM50 N Clear N Clear N N Interrupt acknowledged Interval time Interrupt acknowledged Interval time Remark Interval time = (N + 1) x t N = 00H to FFH 148 User's Manual U15836EJ4V0UD CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50 Figure 7-7. Interval Timer Operation Timing (2/2) (b) When CR50 = 00H t Count clock TM50 00H CR50 TCE50 INTTM50 Interval time 00H 00H 00H 00H (c) When CR50 = FFH t Count clock TM50 CR50 TCE50 INTTM50 Interrupt acknowledged Interval time Interrupt acknowledged FFH 01H FEH FFH FFH 00H FEH FFH FFH 00H User's Manual U15836EJ4V0UD 149 CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50 7.4.2 Operation as external event counter The external event counter counts the number of external clock pulses to be input to TI50 by 8-bit timer counter 50 (TM50). TM50 is incremented each time the valid edge specified by timer clock selection register 50 (TCL50) is input. Either the rising or falling edge can be selected. When the TM50 count value matches the value of 8-bit timer compare register 50 (CR50), TM50 is cleared to 0 and an interrupt request signal (INTTM50) is generated. Whenever the TM50 count value matches the value of CR50, INTTM50 is generated. Setting <1> Set each register. * Set port mode register 1 (PM17) to 1. * TCL50: Select TI50 edge. TI50 falling edge TCL50 = 00H TI50 rising edge TCL50 = 01H * CR50: Compare value disable the timer F/F inversion operation, disable timer output. (TMC50 = 0000xx00B x = Don't care) <2> When TCE50 = 1 is set, the number of pulses input from TI50 is counted. <3> When the values of TM50 and CR50 match, INTTM50 is generated (TM50 is cleared to 00H). <4> After these settings, INTTM50 is generated each time the values of TM50 and CR50 match. Figure 7-8. External Event Counter Operation Timing (with Rising Edge Specified) TI50 Count start TM50 count value CR50 INTTM50 00 01 02 03 04 05 N-1 N N 00 01 02 03 * TMC50: Stop the count operation, select clear & start mode entered on match of TM50 and CR50, N = 00H to FFH 150 User's Manual U15836EJ4V0UD CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50 7.4.3 Operation as square-wave output A square wave with any selected frequency is output at intervals determined by the value preset to 8-bit timer compare register 50 (CR50). The TO50 pin output status is inverted at intervals determined by the count value preset to CR50 by setting bit 0 (TOE50) of 8-bit timer mode control register 50 (TMC50) to 1. This enables a square wave with any selected frequency to be output (duty = 50%). Setting <1> Set each register. * Set the port output latch (P17) and port mode register 1 (PM17) to 0. * TCL50: Select the count clock. * CR50: Compare value * TMC50: Stop the count operation, select clear & start mode entered on a match of TM50 and CR50. LVS50 1 0 LVR50 0 1 Timer Output F/F Status Setting High-level output Low-level output Timer output F/F inversion enabled Timer output enabled (TMC50 = 00001011B or 00000111B) <2> After TCE50 = 1 is set, the count operation starts. <3> The timer output F/F is inverted by a match of TM50 and CR50. After INTTM50 is generated, TM50 is cleared to 00H. <4> After these settings, the timer output F/F is inverted at the same interval and a square wave is output from TO50. The frequency is as follows. Frequency = 1/2t (N + 1) (N: 00H to FFH) Caution Do not write other values to CR50 during operation. Figure 7-9. Square-Wave Output Operation Timing t Count clock TM50 count value 00H 01H 02H N-1 N 00H 01H 02H N-1 N 00H Count start CR50 N TO50Note Note The initial value of TO50 output can be set by bits 2 and 3 (LVR50, LVS50) of 8-bit timer mode control register 50 (TMC50). User's Manual U15836EJ4V0UD 151 CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50 7.4.4 Operation as PWM output 8-bit timer/event counter 50 operates as a PWM output when bit 6 (TMC506) of 8-bit timer mode control register 50 (TMC50) is set to 1. The duty pulse is determined by the value set to 8-bit timer compare register 50 (CR50). Set the active level width of the PWM pulse to CR50; the active level can be selected with bit 1 of TMC50 (TMC501). The count clock can be selected with bits 0 to 2 (TCL500 to TCL502) of timer clock selection register 50 (TCL50). PWM output can be enabled/disabled with bit 0 of TMC50 (TOE50). Caution In PWM mode, make the CR50 rewrite period 3 count clocks of the count clock (clock selected by TCL50) or more. (1) PWM output basic operation Setting <1> Set each register. * Set the port output latch (P17) and port mode register 1 (PM17) to 0. * TCL50: Select the count clock. * CR50: Compare value The timer output F/F is not changed, timer output is enabled. TMC501 0 1 Active-high Active-low Active Level Selection * TMC50: Stop the count operation, select PWM mode. (TMC50 = 01000001B or 01000011B) <2> The count operation starts when TCE50 = 1. Set TCE50 to 0 to stop the count operation. PWM output operation <1> PWM output (output from TO50) outputs an inactive level until an overflow occurs. <2> When an overflow occurs, the active level is output. The active level is output until CR50 matches the count value of 8-bit timer counter 50 (TM50). <3> After the CR50 matches the count value, the inactive level is output until an overflow occurs again. <4> Operations <2> and <3> are repeated until the count operation stops. <5> When the count operation is stopped with TCE50 = 0, PWM output becomes inactive. For details of timing, see Figures 7-10 and 7-11. The cycle, active-level width, and duty are as follows. * Cycle = 28t * Active-level width = Nt * Duty = N/28 (N = 00H to FFH) 152 User's Manual U15836EJ4V0UD CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50 Figure 7-10. PWM Output Operation Timing (a) Basic operation (active level = H) t Count clock TM50 CR50 TCE50 INTTM50 TO50 <1> <2> Active level <3> Inactive level Active level <5> 00H 01H N FFH 00H 01H 02H N N+1 FFH 00H 01H 02H M 00H (b) CR50 = 00H t Count clock TM50 CR50 TCE50 INTTM50 TO50 L Inactive level Inactive level 00H 01H 00H FFH 00H 01H 02H N N+1 N+2 FFH 00H 01H 02H M 00H (c) CR50 = FFH t Count clock TM50 CR50 TCE50 INTTM50 TO50 Inactive level Active level Active level Inactive level Inactive level 00H 01H FFH FFH 00H 01H 02H N N+1 N+2 FFH 00H 01H 02H M 00H Remark <1> to <3> and <5> in Figure 7-10 (a) correspond to <1> to <3> and <5> in PWM output operation in 7.4.4 (1) PWM output basic operation. User's Manual U15836EJ4V0UD 153 CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50 (2) Operation with CR50 changed Figure 7-11. Timing of Operation with CR50 Changed (a) CR50 value is changed from N to M before clock rising edge of FFH Value is transferred to CR50 at overflow immediately after change. t Count clock TM50 CR50 TCE50 INTTM50 TO50 <1> CR50 change (N M) <2> H N N+1 N+2 N FFH 00H 01H 02H M M M+1 M+2 FFH 00H 01H 02H M M+1 M+2 (b) CR50 value is changed from N to M after clock rising edge of FFH Value is transferred to CR50 at second overflow. t Count clock TM50 CR50 TCE50 INTTM50 TO50 <1> CR50 change (N M) <2> H N N+1 N+2 N FFH 00H 01H 02H N N N+1 N+2 FFH 00H 01H 02H M M M+1 M+2 Caution When reading from CR50 between <1> and <2> in Figure 7-11, the value read differs from the actual value (read value: M, actual value of CR50: N). 7.5 Cautions for 8-Bit Timer/Event Counter 50 (1) Timer start error An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 8-bit timer counter 50 (TM50) is started asynchronously to the count clock. Figure 7-12. 8-Bit Timer Counter 50 Start Timing Count clock TM50 count value 00H Timer start 01H 02H 03H 04H 154 User's Manual U15836EJ4V0UD CHAPTER 8 8-BIT TIMERS H0 AND H1 8.1 Functions of 8-Bit Timers H0 and H1 8-bit timers H0 and H1 have the following functions. * Interval timer * PWM output mode * Square-wave output 8.2 Configuration of 8-Bit Timers H0 and H1 8-bit timers H0 and H1 include the following hardware. Table 8-1. Configuration of 8-Bit Timers H0 and H1 Item Timer register Registers 8-bit timer counter Hn 8-bit timer H compare register 0n (CMP0n) 8-bit timer H compare register 1n (CMP1n) Timer outputs Control registers TOHn 8-bit timer H mode register n (TMHMDn) Port mode register 1 (PM1) Port register 1 (P1) Configuration Remark n = 0, 1 Figures 8-1 and 8-2 show the block diagrams. User's Manual U15836EJ4V0UD 155 Selector 156 3 2 Decoder fX fX/2 fX/22 fX/26 fX/210 8-bit timer/ event counter 50 output Figure 8-1. Block Diagram of 8-Bit Timer H0 Internal bus 8-bit timer H mode control register 0 (TMHMD0) TMHE0 CKS02 CKS01 CKS00 TMMD01TMMD00 TOLEV0 TOEN0 8-bit timer H compare register 10 (CMP10) 8-bit timer H compare register 00 (CMP00) TOH0/P15 Selector CHAPTER 8 8-BIT TIMERS H0 AND H1 Match Interrupt generator 8-bit timer counter H0 Clear PWM mode signal 1 0 F/F R Output controller Level inversion Output latch (P15) PM15 User's Manual U15836EJ4V0UD Timer H enable signal INTTMH0 Figure 8-2. Block Diagram of 8-Bit Timer H1 Internal bus 8-bit timer H mode control register 1 (TMHMD1) TMHE1 CKS12 CKS11 CKS10 TMMD11TMMD10 TOLEV1 TOEN1 8-bit timer H compare register 11 (CMP11) 8-bit timer H compare register 01 (CMP01) 3 2 Decoder Selector Match Interrupt generator F/F R TOH1/ INTP5/ P16 fX fX/22 fX/24 fX/26 fX/212 fR/27 Output controller Level inversion Output latch (P16) CHAPTER 8 8-BIT TIMERS H0 AND H1 PM16 User's Manual U15836EJ4V0UD Selector 8-bit timer counter H1 Clear PWM mode signal 1 0 Timer H enable signal INTTMH1 157 CHAPTER 8 8-BIT TIMERS H0 AND H1 (1) 8-bit timer H compare register 0n (CMP0n) This register can be read/written by an 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 8-3. Format of 8-Bit Timer H Compare Register 0n (CMP0n) Address: FF18H (CMP00), FF1AH (CMP01) Symbol CMP0n (n = 0, 1) 7 6 5 4 After reset: 00H 3 R/W 2 1 0 Caution CMP0n cannot be rewritten during timer count operation. (2) 8-bit timer H compare register 1n (CMP1n) This register can be read/written by an 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 8-4. Format of 8-Bit Timer H Compare Register 1n (CMP1n) Address: FF19H (CMP10), FF1BH (CMP11) Symbol CMP1n (n = 0, 1) 7 6 5 4 After reset: 00H 3 R/W 2 1 0 CMP1n can be rewritten during timer count operation. If the CMP1n value is rewritten during timer operation, transfer is performed at the timing at which the counter value and CMP1n value match. performed. Caution In the PWM output mode be sure to set CMP1n when starting the timer count operation (TMHEn = 1) after the timer count operation was stopped (TMHEn = 0) (be sure to set again even if setting the same value to CMP1n). Remark n = 0, 1 If the transfer timing and writing from CPU to CMP1n conflict, transfer is not 158 User's Manual U15836EJ4V0UD CHAPTER 8 8-BIT TIMERS H0 AND H1 8.3 Registers Controlling 8-Bit Timers H0 and H1 The following three registers are used to control 8-bit timers H0 and H1. * 8-bit timer H mode register n (TMHMDn) * Port mode register 1 (PM1) * Port register 1 (P1) (1) 8-bit timer H mode register n (TMHMDn) This register controls the mode of timer H. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Remark n = 0, 1 User's Manual U15836EJ4V0UD 159 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-5. Format of 8-Bit Timer H Mode Register 0 (TMHMD0) Address: FF69H Symbol TMHMD0 <7> TMHE0 After reset: 00H 6 CKS02 R/W 5 CKS01 4 CKS00 3 2 <1> <0> TOEN0 TMMD01 TMMD00 TOLEV0 TMHE0 0 1 Timer operation enable Stops timer count operation (counter is cleared to 0) Enables timer count operation (count operation started by inputting clock) CKS02 0 0 0 0 1 1 CKS01 0 0 1 1 0 0 CKS00 0 1 0 1 0 1 fX fX/2 fX/2 fX/2 2 6 Count clock (fCNT) selection (10 MHz) (5 MHz) (2.5 MHz) (156.25 kHz) (9.77 kHz) fX/210 TM50 outputNote Setting prohibited Other than above TMMD01 TMMD00 0 1 0 0 Interval timer mode PWM output mode Setting prohibited Timer operation mode Other than above TOLEV0 0 1 Low level High level Timer output level control (in default mode) TOEN0 0 1 Disables output Enables output Timer output control Note To select the TM50 output as a count clock, start operation by setting 8-bit timer/event counter 50 in the PWM mode (bit 6 (TMC506) of the TMC50 register = 1), and then set CKS02, CKS01, and CKS00 to 1, 0, and 1, respectively. Set the high/low level width of the count clock so that the specifications of the input width of TI50 are satisfied (refer to AC Characteristics (1) Basic operation in CHAPTER 23 to CHAPTER 25). It is not necessary to enable the TO50 pin as a timer output pin (bit 0 (TOE50) of the TMC register may be 0 or 1). 160 User's Manual U15836EJ4V0UD CHAPTER 8 8-BIT TIMERS H0 AND H1 Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the Ring-OSC oscillator is divided and supplied as the count clock. If the count clock is the Ring-OSC clock, the operation of 8-bit timer H0 is not guaranteed. 2. When TMHE0 = 1, setting the other bits of TMHMD0 is prohibited. 3. In the PWM output mode, be sure to set 8-bit timer H compare register 10 (CMP10) when starting the timer count operation (TMHE0 = 1) after the timer count operation was stopped (TMHE0 = 0) (be sure to set again even if setting the same value to CMP10). Remarks 1. fX: X1 input clock oscillation frequency 2. Figures in parentheses apply to operation at fX = 10 MHz Figure 8-6. Format of 8-Bit Timer H Mode Register 1 (TMHMD1) Address: FF6CH Symbol TMHMD1 <7> TMHE1 After reset: 00H 6 CKS12 R/W 5 CKS11 4 CKS10 3 2 <1> <0> TOEN1 TMMD11 TMMD10 TOLEV1 TMHE1 0 1 Timer operation enable Stops timer count operation (counter is cleared to 0) Enables timer count operation (count operation started by inputting clock) CKS12 0 0 0 0 1 1 CKS11 0 0 1 1 0 0 CKS10 0 1 0 1 0 1 fX fX/2 2 Count clock (fCNT) selection (10 MHz) (2.5 MHz) (625 kHz) (156.25 kHz) (2.44 kHz) (1.88 kHz (TYP.)) fX/24 fX/2 fX/2 6 12 7 fR/2 Other than above Setting prohibited TMMD11 TMMD10 0 1 0 0 Interval timer mode PWM output mode Setting prohibited Timer operation mode Other than above TOLEV1 0 1 Low level High level Timer output level control (in default mode) TOEN1 0 1 Disables output Enables output Timer output control User's Manual U15836EJ4V0UD 161 CHAPTER 8 8-BIT TIMERS H0 AND H1 Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the Ring-OSC oscillator is divided and supplied as the count clock. If the count clock is the Ring-OSC clock, the operation of 8-bit timer H1 is not guaranteed (except when CKS12, CKS11, CKS10 = 1, 0, 1 (fR/27)). 2. When TMHE1 = 1, setting the other bits of TMHMD1 is prohibited. 3. In the PWM output mode, be sure to set 8-bit timer H compare register 11 (CMP11) when starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to CMP11). Remarks 1. fX: X1 input clock oscillation frequency 2. fR: Ring-OSC clock oscillation frequency 3. Figures in parentheses apply to operation at fX = 10 MHz, fR = 240 kHz (TYP.). (2) Port mode register 1 (PM1) This register sets port 1 input/output in 1-bit units. When using the P15/TOH0 and P16/TOH1/INTP5 pins for timer output, clear PM15 and PM16 and the output latches of P15 and P16 to 0. PM1 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to FFH. Figure 8-7. Format of Port Mode Register 1 (PM1) Address: FF21H Symbol PM1 7 PM17 After reset: FFH 6 PM16 R/W 5 PM15 4 PM14 3 PM13 2 PM12 1 PM11 0 PM10 PM1n 0 1 P1n pin I/O mode selection (n = 0 to 7) Output mode (output buffer on) Input mode (output buffer off) 162 User's Manual U15836EJ4V0UD CHAPTER 8 8-BIT TIMERS H0 AND H1 8.4 Operation of 8-Bit Timers H0 and H1 8.4.1 Operation as interval timer/square-wave output When 8-bit timer counter Hn and compare register 0n (CMP0n) match, an interrupt request signal (INTTMHn) is generated and 8-bit timer counter Hn is cleared to 00H. Compare register 1n (CMP1n) is not used in interval timer mode. Since a match of 8-bit timer counter Hn and the CMP1n register is not detected even if the CMP1n register is set, timer output is not affected. By setting bit 0 (TOENn) of timer H mode register n (TMHMDn) to 1, a square wave of any frequency (duty = 50%) is output from TOHn. (1) Usage Generates the INTTMHn signal repeatedly at the same interval. <1> Set each register. Figure 8-8. Register Setting During Interval Timer/Square-Wave Output Operation (i) Setting timer H mode register n (TMHMDn) TMHEn TMHMDn 0 CKSn2 0/1 CKSn1 0/1 CKSn0 0/1 TMMDn1 TMMDn0 TOLEVn 0 0 0/1 TOENn 0/1 Timer output setting Timer output level inversion setting Interval timer mode setting Count clock (fCNT) selection Count operation stopped (ii) CMP0n register setting * Compare value (N) <2> Count operation starts when TMHEn = 1. <3> When the values of 8-bit timer counter Hn and the CMP0n register match, the INTTMHn signal is generated and 8-bit timer counter Hn is cleared to 00H. Interval time = (N +1)/fCNT <4> Subsequently, the INTTMHn signal is generated at the same interval. To stop the count operation, set TMHEn to 0. Remark n = 0, 1 User's Manual U15836EJ4V0UD 163 CHAPTER 8 8-BIT TIMERS H0 AND H1 (2) Timing chart The timing of the interval timer/square-wave output operation is shown below. Figure 8-9. Timing of Interval Timer/Square-Wave Output Operation (1/2) (a) Basic operation Count clock Count start 8-bit timer counter Hn 00H 01H N 00H Clear 01H N 00H Clear 01H 00H CMP0n N TMHEn INTTMHn Interval time TOHn <1> <2> Level inversion, match interrupt occurrence, 8-bit timer counter Hn clear <3> <2> Level inversion, match interrupt occurrence, 8-bit timer counter Hn clear <1> The count operation is enabled by setting the TMHEn bit to 1. The count clock starts counting no more than 1 clock after the operation is enabled. <2> When the values of 8-bit timer counter Hn and the CMP0n register match, the value of 8-bit timer counter Hn is cleared, the TOHn output level is inverted, and the INTTMHn signal is output. <3> The INTTMHn signal and TOHn output become inactive by setting the TMHEn bit to 0 during timer Hn operation. If these are inactive from the first, the level is retained. Remark n = 0, 1 N = 01H to FEH 164 User's Manual U15836EJ4V0UD CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-9. Timing of Interval Timer/Square-Wave Output Operation (2/2) (b) Operation when CMP0n = FFH Count clock Count start 8-bit timer counter Hn 00H 01H FEH FFH 00H Clear FEH FFH 00H Clear CMP0n FFH TMHEn INTTMHn TOHn Interval time (c) Operation when CMP0n = 00H Count clock Count start 8-bit timer counter Hn 00H CMP0n 00H TMHEn INTTMHn TOHn Interval time Remark n = 0, 1 User's Manual U15836EJ4V0UD 165 CHAPTER 8 8-BIT TIMERS H0 AND H1 8.4.2 Operation as PWM output mode In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output. 8-bit timer compare register 0n (CMP0n) controls the cycle of timer output (TOHn). Rewriting the CMP0n register during timer operation is prohibited. 8-bit timer compare register 1n (CMP1n) controls the duty of timer output (TOHn). Rewriting the CMP1n register during timer operation is possible. The operation in PWM output mode is as follows. TOHn output becomes active and 8-bit timer counter Hn is cleared to 0 when 8-bit timer counter Hn and the CMP0n register match after the timer count is started. TOHn output becomes inactive when 8-bit timer counter Hn and the CMP1n register match. (1) Usage In PWM output mode, a pulse for which an arbitrary duty and arbitrary cycle can be set is output. <1> Set each register. Figure 8-10. Register Setting in PWM Output Mode (i) Setting timer H mode register n (TMHMDn) CKSn2 0/1 CKSn1 0/1 CKSn0 0/1 TMMDn1 TMMDn0 TOLEVn 1 0 0/1 TOENn 1 TMHEn TMHMDn 0 Timer output enabled Timer output level inversion setting PWM output mode selection Count clock (fCNT) selection Count operation stopped (ii) Setting CMP0n register * Compare value (N): Cycle setting (iii) Setting CMP1n register * Compare value (M): Duty setting Remarks 1. n = 0, 1 2. 00H CMP1n (M) < CMP0n (N) FFH <2> The count operation starts when TMHEn = 1. <3> The CMP0n register is the compare register that is to be compared first after counter operation is enabled. When the values of 8-bit timer counter Hn and the CMP0n register match, 8-bit timer counter Hn is cleared, an interrupt request signal (INTTMHn) is generated, and TOHn output becomes active. At the same time, the compare register to be compared with 8-bit timer counter Hn is changed from the CMP0n register to the CMP1n register. 166 User's Manual U15836EJ4V0UD CHAPTER 8 8-BIT TIMERS H0 AND H1 <4> When 8-bit timer counter Hn and the CMP1n register match, TOHn output becomes inactive and the compare register to be compared with 8-bit timer counter Hn is changed from the CMP1n register to the CMP0n register. generated. <5> By performing procedures <3> and <4> repeatedly, a pulse with an arbitrary duty can be obtained. <6> To stop the count operation, set TMHEn = 0. If the setting value of the CMP0n register is N, the setting value of the CMP1n register is M, and the count clock frequency is fCNT, the PWM pulse output cycle and duty are as follows. PWM pulse output cycle = (N+1)/fCNT Duty = Active width : Total width of PWM = (M + 1) : (N + 1) At this time, 8-bit timer counter Hn is not cleared and the INTTMHn signal is not Cautions 1. In PWM output mode, three operation clocks (signal selected using the CKSn2 to CKSn0 bits of the TMHMDn register) are required to transfer the CMP1n register value after rewriting the register. 2. Be sure to set the CMP1n register when starting the timer count operation (TMHEn = 1) after the timer count operation was stopped (TMHEn = 0) (be sure to set again even if setting the same value to the CMP1n register). User's Manual U15836EJ4V0UD 167 CHAPTER 8 8-BIT TIMERS H0 AND H1 (2) Timing chart The operation timing in PWM output mode is shown below. Caution Make sure that the CMP1n register setting value (M) and CMP0n register setting value (N) are within the following range. 00H CMP1n (M) < CMP0n (N) FFH Remark n = 0, 1 Figure 8-11. Operation Timing in PWM Output Mode (1/4) (a) Basic operation Count clock 8-bit timer counter Hn 00H 01H A5H 00H 01H 02H A5H 00H 01H 02H A5H 00H CMP0n A5H CMP1n 01H TMHEn INTTMHn TOHn (TOLEVn = 0) <1> TOHn (TOLEVn = 1) <2> <3> <4> <1> The count operation is enabled by setting the TMHEn bit to 1. Start 8-bit timer counter Hn by masking one count clock to count up. At this time, TOHn output remains inactive (when TOLEVn = 0). <2> When the values of 8-bit timer counter Hn and the CMP0n register match, the TOHn output level is inverted, the value of 8-bit timer counter Hn is cleared, and the INTTMHn signal is output. <3> When the values of 8-bit timer counter Hn and the CMP1n register match, the level of the TOHn output is returned. At this time, the 8-bit timer counter value is not cleared and the INTTMHn signal is not output. <4> Setting the TMHEn bit to 0 during timer Hn operation makes the INTTMHn signal and TOHn output inactive. Remark n = 0, 1 168 User's Manual U15836EJ4V0UD CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-11. Operation Timing in PWM Output Mode (2/4) (b) Operation when CMP0n = FFH, CMP1n = 00H Count clock 8-bit timer counter Hn 00H 01H FFH 00H 01H 02H FFH 00H 01H 02H FFH 00H CMP0n FFH CMP1n 00H TMHEn INTTMHn TOHn (TOLEVn = 0) (c) Operation when CMP0n = FFH, CMP1n = FEH Count clock 8-bit timer counter Hn 00H 01H FEH FFH 00H 01H FEH FFH 00H 01H FEH FFH 00H CMP0n FFH CMP1n FEH TMHEn INTTMHn TOHn (TOLEVn = 0) Remark n = 0, 1 User's Manual U15836EJ4V0UD 169 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-11. Operation Timing in PWM Output Mode (3/4) (d) Operation when CMP0n = 01H, CMP1n = 00H Count clock 8-bit timer counter Hn 00H 01H 00H 01H 00H 00H 01H 00H 01H CMP0n 01H CMP1n 00H TMHEn INTTMHn TOHn (TOLEVn = 0) Remark n = 0, 1 170 User's Manual U15836EJ4V0UD CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-11. Operation Timing in PWM Output Mode (4/4) (e) Operation by changing CMP1n (CMP1n = 01H 03H, CMP0n = A5H) Count clock 8-bit timer counter Hn 00H 01H 02H A5H 00H 01H 02H 03H A5H 00H 01H 02H 03H A5H 00H CMP0n A5H CMP1n 01H <2> 01H (03H) <2>' 03H TMHEn INTTMHn TOHn (TOLEVn = 0) <1> <3> <4> <5> <6> <1> The count operation is enabled by setting TMHEn = 1. Start 8-bit timer counter Hn by masking one count clock to count up. At this time, the TOHn output remains inactive (when TOLEVn = 0). <2> The CMP1n register value can be changed during timer counter operation. This operation is asynchronous to the count clock. <3> When the values of 8-bit timer counter Hn and the CMP0n register match, the value of 8-bit timer counter Hn is cleared, the TOHn output becomes active, and the INTTMHn signal is output. <4> If the CMP1n register value is changed, the value is latched and not transferred to the register. When the values of 8-bit timer counter Hn and the CMP1n register before the change match, the value is transferred to the CMP1n register and the CMP1n register value is changed (<2>'). However, three count clocks or more are required from when the CMP1n register value is changed to when the value is transferred to the register. If a match signal is generated within three count clocks, the changed value cannot be transferred to the register. <5> When the values of 8-bit timer counter Hn and the CMP1n register after the change match, the TOHn output becomes inactive. 8-bit timer counter Hn is not cleared and the INTTMHn signal is not generated. <6> Setting the TMHEn bit to 0 during timer Hn operation makes the INTTMHn signal and TOHn output inactive. Remark n = 0, 1 User's Manual U15836EJ4V0UD 171 CHAPTER 9 WATCHDOG TIMER 9.1 Functions of Watchdog Timer The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated. When a reset occurs due to the watchdog timer, bit 4 (WDTRF) of the reset control flag register (RESF) is set to 1. For details of RESF, see CHAPTER 16 RESET FUNCTION. Table 9-1. Loop Detection Time of Watchdog Timer Loop Detection Time During Ring-OSC Clock Operation fR/2 (8.53 ms) fR/2 (17.07 ms) fR/2 (34.13 ms) fR/2 (68.27 ms) fR/2 (136.53 ms) fR/2 (273.07 ms) fR/2 (546.13 ms) fR/2 (1.09 s) 18 17 16 15 14 13 12 11 During X1 Input Clock Operation fXP/2 (819.2 s) 13 fXP/2 (1.64 ms) fXP/2 (3.28 ms) fXP/2 (6.55 ms) fXP/2 (13.11 ms) fXP/2 (26.21 ms) fXP/2 (52.43 ms) fXP/2 (104.86 ms) 20 19 18 17 16 15 14 Remarks 1. fR: Ring-OSC clock oscillation frequency 2. fXP: X1 input clock oscillation frequency 3. Figures in parentheses apply to operation at fR = 240 kHz (TYP.), fXP = 10 MHz The operation mode of the watchdog timer (WDT) is switched according to the mask option setting of the on-chip Ring-OSC as shown in Table 9-2. 172 User's Manual U15836EJ4V0UD CHAPTER 9 WATCHDOG TIMER Table 9-2. Mask Option Setting and Watchdog Timer Operation Mode Mask Option Ring-OSC Cannot Be Stopped Watchdog timer clock source Fixed to fR Note 1 Ring-OSC Can Be Stopped by Software * Selectable by software (fXP, fR or stopped) * When reset is released: fR . Operation after reset Operation starts with the maximum interval (fR/2 ). 18 Operation starts with maximum interval (fR/2 ). The clock selection/interval can be changed only once. The watchdog timer can be stopped in standby mode Note 2 18 Operation mode selection The interval can be changed only once. Features The watchdog timer cannot be stopped. . Notes 1. 2. As long as power is being supplied, Ring-OSC oscillation cannot be stopped (except in the reset period). The conditions under which clock supply to the watchdog timer is stopped differ depending on the clock source of the watchdog timer. <1> If the clock source is fXP, clock supply to the watchdog timer is stopped under the following conditions. * When fXP is stopped * In HALT/STOP mode * During oscillation stabilization time <2> If the clock source is fR, clock supply to the watchdog timer is stopped under the following conditions. * If the CPU clock is fXP and if fR is stopped by software before execution of the STOP instruction * In HALT/STOP mode Remarks 1. fR: Ring-OSC clock oscillation frequency 2. fXP: X1 input clock oscillation frequency User's Manual U15836EJ4V0UD 173 CHAPTER 9 WATCHDOG TIMER 9.2 Configuration of Watchdog Timer The watchdog timer includes the following hardware. Table 9-3. Configuration of Watchdog Timer Item Control registers Configuration Watchdog timer mode register (WDTM) Watchdog timer enable register (WDTE) Figure 9-1. Block Diagram of Watchdog Timer fR/22 fXP/2 4 Clock input controller 2 fR/211 to fR/218 16-bit counter Selector or fXP/213 to fXP/220 3 Output controller Internal reset signal Clear 3 Watchdog timer enable register (WDTE) 0 1 1 WDCS4 WDCS3 WDCS2 WDCS1 WDCS0 Watchdog timer mode register (WDTM) Internal bus Mask option (to set "Ring-OSC cannot be stopped" or "Ring-OSC can be stopped by software") 174 User's Manual U15836EJ4V0UD CHAPTER 9 WATCHDOG TIMER 9.3 Registers Controlling Watchdog Timer The watchdog timer is controlled by the following two registers. * Watchdog timer mode register (WDTM) * Watchdog timer enable register (WDTE) (1) Watchdog timer mode register (WDTM) This register sets the overflow time and operation clock of the watchdog timer. This register can be set by an 8-bit memory manipulation instruction and can be read many times, but can be written only once after reset is released. RESET input sets this register to 67H. Figure 9-2. Format of Watchdog Timer Mode Register (WDTM) Address: FF98H Symbol WDTM 7 0 After reset: 67H 6 1 R/W 5 1 4 WDCS4 3 WDCS3 2 WDCS2 1 WDCS1 0 WDCS0 WDCS4 0 0 1 Note 1 WDCS3 0 1 x Note 1 Operation clock selection Ring-OSC clock (fR) X1 input clock (fXP) Watchdog timer operation stopped WDCS2 Note 2 WDCS1 Note 2 WDCS0 Note 2 Overflow time setting During Ring-OSC clock operation 11 During X1 input clock operation fXP/2 (819.2 s) 13 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fR/2 (8.53 ms) fR/2 (17.07 ms) fR/2 (34.13 ms) fR/2 (68.27 ms) fR/2 (136.53 ms) fR/2 (273.07 ms) fR/2 (546.13 ms) fR/2 (1.09 s) 18 17 16 15 14 13 12 fXP/2 (1.64 ms) fXP/2 (3.28 ms) fXP/2 (6.55 ms) fXP/2 (13.11 ms) fXP/2 (26.21 ms) fXP/2 (52.43 ms) fXP/2 (104.86 ms) 20 19 18 17 16 15 14 Notes 1. 2. If "Ring-OSC cannot be stopped" is specified by a mask option, this cannot be set. The RingOSC clock will be selected no matter what value is written. Reset is released at the maximum cycle (WDCS2, 1, 0 = 1, 1, 1). Cautions 1. If data is written to WDTM, a wait cycle is generated. For details, see CHAPTER 28 CAUTIONS FOR WAIT. 2. Set bits 7, 6, and 5 to 0, 1, and 1, respectively (when "Ring-OSC cannot be stopped" is selected by a mask option, other values are ignored). User's Manual U15836EJ4V0UD 175 CHAPTER 9 WATCHDOG TIMER Cautions 3. After reset is released, WDTM can be written only once by an 8-bit memory manipulation instruction. If writing is attempted a second time, an internal reset signal is generated. 4. WDTM cannot be set by a 1-bit memory manipulation instruction. Remarks 1. fR: Ring-OSC clock oscillation frequency 2. fXP: X1 input clock oscillation frequency 3. x: Don't care 4. Figures in parentheses apply to operation at fR = 240 kHz (TYP.), fXP = 10 MHz (2) Watchdog timer enable register (WDTE) Writing ACH to WDTE clears the watchdog timer counter and starts counting again. This register can be set by an 8-bit memory manipulation instruction. RESET input sets this register to 9AH. Figure 9-3. Format of Watchdog Timer Enable Register (WDTE) Address: FF99H Symbol WDTE 7 After reset: 9AH 6 R/W 5 4 3 2 1 0 Cautions 1. If a value other than ACH is written to WDTE, an internal reset signal is generated. 2. If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset signal is generated. 3. The value read from WDTE is 9AH (this differs from the written value (ACH)). 176 User's Manual U15836EJ4V0UD CHAPTER 9 WATCHDOG TIMER 9.4 Operation of Watchdog Timer 9.4.1 Watchdog timer operation when "Ring-OSC cannot be stopped" is selected by mask option The operation clock of watchdog timer is fixed to Ring-OSC. After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of the watchdog timer mode register (WDTM) = 1, 1, 1). The watchdog timer operation cannot be stopped. The following shows the watchdog timer operation after reset release. 1. The status after reset release is as follows. * Operation clock: Ring-OSC clock * Cycle: fR/218 (1.09 seconds: At operation with fR = 240 kHz (TYP.)) * Counting starts 2. The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation instructionNotes 1, 2. * Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0) 3. After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting. The operation clock (Ring-OSC clock) cannot be changed. If any value is written to bits 3 and 4 (WDCS3, WDCS4) of WDTM, it is ignored. 2. As soon as WDTM is written, the counter of the watchdog timer is cleared. Notes 1. Caution In this mode, operation of the watchdog timer absolutely cannot be stopped even during STOP instruction execution. For 8-bit timer H1 (TMH1), a division of the Ring-OSC can be selected as the count source, so after STOP instruction execution, clear the watchdog timer using the interrupt request of TMH1 before the watchdog timer overflows. instruction execution. If this processing is not performed, an internal reset signal is generated when the watchdog timer overflows after STOP User's Manual U15836EJ4V0UD 177 CHAPTER 9 WATCHDOG TIMER 9.4.2 Watchdog timer operation when "Ring-OSC can be stopped by software" is selected by mask option The operation clock of the watchdog timer can be selected as either the Ring-OSC clock or the X1 input clock. After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of the watchdog timer mode register (WDTM) = 1, 1, 1) of the Ring-OSC clock. The following shows the watchdog timer operation after reset release. 1. The status after reset release is as follows. * Operation clock: Ring-OSC clock oscillation frequency (fR) * Cycle: fR/218 (1.09 seconds: At operation with fR = 240 kHz (TYP.)) * Counting starts 2. The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation instructionNotes 1, 2, 3. * Operation clock: Any of the following can be selected using bits 3 and 4 (WDCS3 and WDCS4). Ring-OSC clock (fR) X1 input clock (fXP) Watchdog timer operation stopped * Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0) 3. After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting. As soon as WDTM is written, the counter of the watchdog timer is cleared. Set bits 7, 6, and 5 to 0, 1, 1, respectively. These bits must not be set to other values. If the watchdog timer is stopped by setting WDCS4 and WDCS3 to 1 and x, respectively, an internal reset signal is not generated even if the following processing is performed. * WDTM is written a second time. * A 1-bit memory manipulation instruction is executed to WDTE. * A value other than ACH is written to WDTE. Caution In this mode, watchdog timer operation is stopped during HALT/STOP instruction execution. After HALT/STOP mode is released, counting is started again using the operation clock of the watchdog timer set before HALT/STOP instruction execution by WDTM. At this time, the counter is not cleared to 0 but holds its value. For the watchdog timer operation during STOP mode and HALT mode in each status, see 9.4.3 Watchdog timer operation in STOP mode and 9.4.4 Watchdog timer operation in HALT mode. Notes 1. 2. 3. 178 User's Manual U15836EJ4V0UD CHAPTER 9 WATCHDOG TIMER 9.4.3 Watchdog timer operation in STOP mode (when "Ring-OSC can be stopped by software" is selected by mask option) The watchdog timer stops counting during STOP instruction execution regardless of whether the X1 input clock or Ring-OSC clock is being used. (1) When the CPU clock and the watchdog timer operation clock are the X1 input clock (fXP) when the STOP instruction is executed When STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released, counting stops for the oscillation stabilization time set by the oscillation stabilization time select register (OSTS) and then counting is started again using the operation clock before the operation was stopped. At this time, the counter is not cleared to 0 but holds its value. Figure 9-4. Operation in STOP Mode (CPU Clock and WDT Operation Clock: X1 Input Clock) Normal operation CPU operation fXP STOP Oscillation stabilization time Normal operation Oscillation stopped fR Watchdog timer Oscillation stabilization time (set by OSTS register) Operating Operation stopped Operating (2) When the CPU clock is the X1 input clock (fXP) and the watchdog timer operation clock is the Ring-OSC clock (fR) when the STOP instruction is executed When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released, counting is started again using the operation clock before the operation was stopped. At this time, the counter is not cleared to 0 but holds its value. Figure 9-5. Operation in STOP Mode (CPU Clock: X1 Input Clock, WDT Operation Clock: Ring-OSC Clock) Normal operation CPU operation fXP STOP Oscillation stabilization time Normal operation Oscillation stopped fR Watchdog timer Oscillation stabilization time (set by OSTS register) Operating Operation stopped Operating User's Manual U15836EJ4V0UD 179 CHAPTER 9 WATCHDOG TIMER (3) When the CPU clock is the Ring-OSC clock (fR) and the watchdog timer operation clock is the X1 input clock (fXP) when the STOP instruction is executed When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released, counting is stopped until the timing of <1> or <2>, whichever is earlier, and then counting is started using the operation clock before the operation was stopped. At this time, the counter is not cleared to 0 but holds its value. <1> The oscillation stabilization time set by the oscillation stabilization time select register (OSTS) elapses. <2> The CPU clock is switched to the X1 input clock (fXP). Figure 9-6. Operation in STOP Mode (CPU Clock: Ring-OSC Clock, WDT Operation Clock: X1 Input Clock) <1> Timing when counting is started after the oscillation stabilization time set by the oscillation stabilization time select register (OSTS) has elapsed Normal operation CPU operation (Ring-OSC clock) fXP Oscillation stopped fR 17 clocks Watchdog timer Operating Operation stopped Operating Oscillation stabilization time (set by OSTS register) STOP Clock supply stopped Normal operation (Ring-OSC clock) <2> Timing when counting is started after the CPU clock is switched to the X1 input clock (fXP) Normal operation (Ring-OSC clock) Normal operation CPU operation (Ring-OSC clock) fXP Oscillation stopped fR 17 clocks Watchdog timer Operating Operation stopped Operating Oscillation stabilization time (set by OSTS register) Clock supply stopped CPU clock fR fXPNote STOP Normal operation (X1 input clock) Note Confirm the oscillation stabilization time of fXP using the oscillation stabilization time counter status register (OSTC). 180 User's Manual U15836EJ4V0UD CHAPTER 9 WATCHDOG TIMER (4) When CPU clock and watchdog timer operation clock are the Ring-OSC clocks (fR) during STOP instruction execution When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released, counting is started again using the operation clock before the operation was stopped. At this time, the counter is not cleared to 0 but holds its value. Figure 9-7. Operation in STOP Mode (CPU Clock and WDT Operation Clock: Ring-OSC Clock) Normal operation CPU operation (Ring-OSC clock) fXP Oscillation stopped fR 17 clocks Watchdog timer Operating Operation stopped Operating Oscillation stabilization time (set by OSTS register) STOP Clock supply stopped Normal operation (Ring-OSC clock) 9.4.4 Watchdog timer operation in HALT mode (when "Ring-OSC can be stopped by software" is selected by mask option) The watchdog timer stops counting during HALT instruction execution regardless of whether the CPU clock is the X1 input clock (fXP) or Ring-OSC clock (fR), or whether the operation clock of the watchdog timer is the X1 input clock (fXP) or Ring-OSC clock (fR). After HALT mode is released, counting is started again using the operation clock before the operation was stopped. At this time, the counter is not cleared to 0 but holds its value. Figure 9-8. Operation in HALT Mode CPU operation Normal operation fXP HALT Normal operation fR Watchdog timer Operating Operation stopped Operating User's Manual U15836EJ4V0UD 181 CHAPTER 10 A/D CONVERTER 10.1 Function of A/D Converter The A/D converter converts an analog input signal into a digital value, and consists of up to four channels (ANI0 to ANI3) with a resolution of 10 bits. The A/D converter has the following two functions. (1) 10-bit resolution A/D conversion 10-bit resolution A/D conversion is carried out repeatedly for one channel selected from analog inputs ANI0 to ANI3. Each time an A/D conversion operation ends, an interrupt request (INTAD) is generated. (2) Power-fail detection function This function is to detect a voltage drop in a battery. The values of the A/D conversion result (ADCR register value) and power-fail comparison threshold register (PFT) are compared. INTAD is generated only when a comparative condition has been matched. Figure 10-1. Block Diagram of A/D Converter AVREF ADCS bit ANI0/P20 ANI1/P21 ANI2/P22 ANI3/P23 Sample & hold circuit Selector AVSS Successive approximation register (SAR) Tap selector Voltage comparator AVSS INTAD Controller Comparator 2 A/D conversion result register (ADCR) Power-fail comparison threshold register (PFT) ADS1 ADS0 ADCS FR2 FR1 FR0 ADCE PFEN PFCM Analog input channel specification register (ADS) A/D converter mode register (ADM) Internal bus Power-fail comparison mode register (PFM) 182 User's Manual U15836EJ4V0UD CHAPTER 10 A/D CONVERTER 10.2 Configuration of A/D Converter The A/D converter includes the following hardware. Table 10-1. Registers of A/D Converter Used on Software Item Registers Configuration Successive approximation register (SAR) A/D conversion result register (ADCR) A/D converter mode register (ADM) Analog input channel specification register (ADS) Power-fail comparison mode register (PFM) Power-fail comparison threshold register (PFT) (1) ANI0 to ANI3 pins These are the analog input pins of the 4-channel A/D converter. They input analog signals to be converted into digital signals. Pins other than the one selected as the analog input pin by the analog input channel specification register (ADS) can be used as input port pins. (2) Sample & hold circuit The sample & hold circuit samples the input signal of the analog input pin selected by the selector when A/D conversion is started, and holds the sampled analog input voltage value during A/D conversion. (3) Series resistor string The series resistor string is connected between AVREF and AVSS, and generates a voltage to be compared with the analog input signal. (4) Voltage comparator The voltage comparator compares the sampled analog input voltage and the output voltage of the series resistor string. (5) Successive approximation register (SAR) This register compares the sampled analog voltage and the voltage of the series resistor string, and converts the result, starting from the most significant bit (MSB). When the voltage value is converted into a digital value down to the least significant bit (LSB) (end of A/D conversion), the contents of the SAR register are transferred to the A/D conversion result register (ADCR). (6) A/D conversion result register (ADCR) The result of A/D conversion is loaded from the successive approximation register (SAR) to this register each time A/D conversion is completed, and the ADCR register holds the result of A/D conversion in its higher 10 bits (the lower 6 bits are fixed to 0). (7) Controller When A/D conversion has been completed or when the power-fail detection function is used, this controller compares the result of A/D conversion (value of the ADCR register) and the value of the power-fail comparison threshold register (PFT). It generates the interrupt INTAD only if a specified comparison condition is satisfied as a result. User's Manual U15836EJ4V0UD 183 CHAPTER 10 A/D CONVERTER (8) AVREF pin This pin inputs an analog power/reference voltage to the A/D converter. Always use this pin at the same potential as that of the VDD pin even when the A/D converter is not used. The signal input to ANI0 to ANI3 is converted into a digital signal, based on the voltage applied across AVREF and AVSS. In the standby mode, the current flowing through the series resistor string can be reduced by lowering the voltage input to the AVREF pin to the AVSS level. (9) AVSS pin This is the ground potential pin of the A/D converter. Always use this pin at the same potential as that of the VSS pin even when the A/D converter is not used. (10) A/D converter mode register (ADM) This register is used to set the conversion time of the analog input signal to be converted, and to start or stop the conversion operation. (11) Analog input channel specification register (ADS) This register is used to specify the port that inputs the analog voltage to be converted into a digital signal. (12) Power-fail comparison mode register (PFM) This register is used to set the power-fail monitor mode. (13) Power-fail comparison threshold register (PFT) This register is used to set the threshold value that is to be compared with the value of the A/D conversion result register (ADCR). 184 User's Manual U15836EJ4V0UD CHAPTER 10 A/D CONVERTER 10.3 Registers Used in A/D Converter The A/D converter uses the following five registers. * A/D converter mode register (ADM) * Analog input channel specification register (ADS) * A/D conversion result register (ADCR) * Power-fail comparison mode register (PFM) * Power-fail comparison threshold register (PFT) (1) A/D converter mode register (ADM) This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion. ADM can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 10-2. Format of A/D Converter Mode Register (ADM) Address: FF28H Symbol ADM <7> ADCS After reset: 00H 6 0 5 FR2 R/W 4 FR1 3 FR0 2 0 1 0 <0> ADCE ADCS 0 1 A/D conversion operation control Stops conversion operation Enables conversion operation FR2 FR1 FR0 Conversion time selectionNote 1 fX = 2 MHz fX = 8.38 MHz fX = 10 MHz 144 s 120 s 96 s 72 s 60 s 48 s 0 0 0 1 1 1 0 0 1 0 0 1 0 1 0 0 1 0 288/fX 240/fX 192/fX 144/fX 120/fX 96/fX 34.3 s 28.6 s 22.9 s 17.2 s 14.3 s 11.5 s 28.8 s 24.0 s 19.2 s 14.4 s 12.0 s 9.6 s Other than above Setting prohibited ADCE 0 1 Boost reference voltage generator operation controlNote 2 Stops operation of reference voltage generator Enables operation of reference voltage generator Notes 1. Set so that the A/D conversion time is as follows. * Standard products, (A) grade products: 14 s or longer but less than 100 s * (A1) grade products: * (A2) grade products: 14 s or longer but less than 60 s 16 s or longer but less than 48 s User's Manual U15836EJ4V0UD 185 CHAPTER 10 A/D CONVERTER Notes 2. A booster circuit is incorporated to realize low-voltage operation. The operation of the circuit that generates the reference voltage for boosting is controlled by ADCE, and it takes 14 s from operation start to operation stabilization. Therefore, when ADCS is set to 1 after 14 s or more has elapsed from the time ADCE is set to 1, the conversion result at that time has priority over the first conversion result. Remark fX: X1 input clock oscillation frequency Table 10-2. Settings of ADCS and ADCE ADCS 0 0 1 1 ADCE 0 1 0 1 A/D Conversion Operation Stop status (DC power consumption path does not exist) Conversion waiting mode (only reference voltage generator consumes power) Conversion mode (reference voltage generator operation stopped Conversion mode (reference voltage generator operates) Note ) Note Data of first conversion cannot be used. Figure 10-3. Timing Chart When Boost Reference Voltage Generator Is Used Boost reference voltage generator: operating ADCE Boost reference voltage Conversion operation ADCS Note Conversion waiting Conversion operation Conversion stopped Note The time from the rising of the ADCE bit to the falling of the ADCS bit must be 14 s or longer to stabilize the reference voltage. Cautions 1. A/D conversion must be stopped before rewriting bits FR0 to FR2 to values other than the identical data. 2. For the sampling time of the A/D converter and the A/D conversion start delay time, see (11) in 10.6 Cautions for A/D Converter. 3. If data is written to ADM, a wait cycle is generated. For details, see CHAPTER 28 CAUTIONS FOR WAIT. Remark fX: X1 input clock oscillation frequency 186 User's Manual U15836EJ4V0UD CHAPTER 10 A/D CONVERTER (2) Analog input channel specification register (ADS) This register specifies the analog voltage input port to be A/D converted. ADS can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 10-4. Format of Analog Input Channel Specification Register (ADS) Address: FF29H Symbol ADS 7 0 After reset: 00H 6 0 5 0 R/W 4 0 3 0 2 0 1 ADS1 0 ADS0 ADS1 0 0 1 1 ADS0 0 1 0 1 ANI0 ANI1 ANI2 ANI3 Analog input channel specification Cautions 1. Be sure to clear bits 2 to 7 of ADS to 0. 2. If data is written to ADS, a wait cycle is generated. CAUTIONS FOR WAIT. (3) A/D conversion result register (ADCR) This register is a 16-bit register that stores the A/D conversion result. The lower six bits are fixed to 0. Each time A/D conversion ends, the conversion result is loaded from the successive approximation register, and is stored in ADCR in order starting from the most significant bit (MSB). FF09H indicates the higher 8 bits of the conversion result, and FF08H indicates the lower 2 bits of the conversion result. ADCR can be read by a 16-bit memory manipulation instruction. RESET input makes ADCR undefined. Figure 10-5. Format of A/D Conversion Result Register (ADCR) Address: FF08H, FF09H Symbol ADCR After reset: Undefined FF09H R FF08H For details, see CHAPTER 28 0 0 0 0 0 0 Cautions 1. When writing to the A/D converter mode register (ADM) and analog input channel specification register (ADS), the contents of ADCR may become undefined. timing other than the above may cause an incorrect conversion result to be read. 2. If data is read from ADCR, a wait cycle is generated. CAUTIONS FOR WAIT. For details, see CHAPTER 28 Read the conversion result following conversion completion before writing to ADM and ADS. Using User's Manual U15836EJ4V0UD 187 CHAPTER 10 A/D CONVERTER (4) Power-fail comparison mode register (PFM) The power-fail comparison mode register (PFM) is used to compare the A/D conversion result (value of the ADCR register) and the value of the power-fail comparison threshold value register (PFT). PFM can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 10-6. Format of Power-Fail Comparison Mode Register (PFM) Address: FF2AH Symbol PFM <7> PFEN After reset: 00H <6> PFCM 5 0 R/W 4 0 3 0 2 0 1 0 0 0 PFEN 0 1 Power-fail comparison enable Stops power-fail comparison (used as a normal A/D converter) Enables power-fail comparison (used for power-fail detection) PFCM Higher 8 bits of ADCR PFT Higher 8 bits of ADCR < PFT Higher 8 bits of ADCR PFT Higher 8 bits of ADCR < PFT Power-fail comparison mode selection Interrupt request signal (INTAD) generation No INTAD generation No INTAD generation INTAD generation 0 1 Caution If data is written to PFM, a wait cycle is generated. For details, see CHAPTER 28 CAUTIONS FOR WAIT. (5) Power-fail comparison threshold register (PFT) The power-fail comparison threshold register (PFT) is a register that sets the threshold value when comparing the values with the A/D conversion result. 8-bit data in PFT is compared to the higher 8 bits (FF09H) of the 10-bit A/D conversion result. PFT can be set by an 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 10-7. Format of Power-Fail Comparison Threshold Register (PFT) Address: FF2BH Symbol PFT 7 PFT7 After reset: 00H 6 PFT6 5 PFT5 R/W 4 PFT4 3 PFT3 2 PFT2 1 PFT1 0 PFT0 Caution If data is written to PFT, a wait cycle is generated. For details, see CHAPTER 28 CAUTIONS FOR WAIT. 188 User's Manual U15836EJ4V0UD CHAPTER 10 A/D CONVERTER 10.4 A/D Converter Operations 10.4.1 Basic operations of A/D converter <1> Select one channel for A/D conversion using the analog input channel specification register (ADS). <2> Set ADCE to 1 and wait for 14 s or longer. <3> Set ADCS to 1 and start the conversion operation. (<4> to <10> are operations performed by hardware.) <4> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <5> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the input analog voltage is held until the A/D conversion operation has ended. <6> Bit 9 of the successive approximation register (SAR) is set. The series resistor string voltage tap is set to (1/2) AVREF by the tap selector. <7> The voltage difference between the series resistor string voltage tap and analog input is compared by the voltage comparator. If the analog input is greater than (1/2) AVREF, the MSB of SAR remains set to 1. If the analog input is smaller than (1/2) AVREF, the MSB is reset to 0. <8> Next, bit 8 of SAR is automatically set to 1, and the operation proceeds to the next comparison. The series resistor string voltage tap is selected according to the preset value of bit 9, as described below. * Bit 9 = 1: (3/4) AVREF * Bit 9 = 0: (1/4) AVREF The voltage tap and analog input voltage are compared and bit 8 of SAR is manipulated as follows. * Analog input voltage Voltage tap: Bit 8 = 1 * Analog input voltage < Voltage tap: Bit 8 = 0 <9> Comparison is continued in this way up to bit 0 of SAR. <10> Upon completion of the comparison of 10 bits, an effective digital result value remains in SAR, and the result value is transferred to the A/D conversion result register (ADCR) and then latched. At the same time, the A/D conversion end interrupt request (INTAD) can also be generated. <11> Repeat steps <4> to <10>, until ADCS is cleared to 0. To stop the A/D converter, clear ADCS to 0. To restart A/D conversion from the status of ADCE = 1, start from <3>. To restart A/D conversion from the status of ADCE = 0, however, start from <2>. User's Manual U15836EJ4V0UD 189 CHAPTER 10 A/D CONVERTER Figure 10-8. Basic Operation of A/D Converter Conversion time Sampling time A/D converter operation Sampling A/D conversion SAR Undefined Conversion result ADCR Conversion result INTAD A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM) is reset (0) by software. If any of ADM, the analog input channel specification register (ADS), power-fail comparison mode register (PFM), or power-fail comparison threshold register (PFT) is written during an A/D conversion operation, the conversion operation is initialized, and if the ADCS bit is set (1), conversion starts again from the beginning. RESET input makes the A/D conversion result register (ADCR) undefined. 190 User's Manual U15836EJ4V0UD CHAPTER 10 A/D CONVERTER 10.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI3) and the theoretical A/D conversion result (stored in the A/D conversion result register (ADCR)) is shown by the following expression. SAR = INT ( VAIN AVREF x 1024 + 0.5) ADCR = SAR x 64 or (ADCR - 0.5) x where, INT( ): VAIN: AVREF: SAR: AVREF 1024 VAIN < (ADCR + 0.5) x AVREF 1024 Function which returns integer part of value in parentheses Analog input voltage AVREF pin voltage Successive approximation register ADCR: A/D conversion result register (ADCR) value Figure 10-9 shows the relationship between the analog input voltage and the A/D conversion result. Figure 10-9. Relationship Between Analog Input Voltage and A/D Conversion Result SAR ADCR 1023 FFC0H 1022 FF80H 1021 A/D conversion result (ADCR) 3 FF40H 00C0H 2 0080H 1 0040H 0 1 1 3 2 5 3 2048 1024 2048 1024 2048 1024 2043 1022 2045 1023 2047 1 2048 1024 2048 1024 2048 0000H Input voltage/AVREF User's Manual U15836EJ4V0UD 191 CHAPTER 10 A/D CONVERTER 10.4.3 A/D converter operation mode The operation mode of the A/D converter is the select mode. One analog input channel is selected from ANI0 to ANI3 by the analog input channel specification register (ADS) and A/D conversion is executed. In addition, the following two functions can be selected by setting bit 7 (PFEN) of the power-fail comparison mode register (PFM). * Normal 10-bit A/D converter (PFEN = 0) * Power-fail detection function (PFEN = 1) (1) A/D conversion operation (when PFEN = 0) By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1 and bit 7 (PFEN) of the power-fail comparison mode register (PFM) to 0, A/D conversion of the voltage applied to the analog input pin specified by the analog input channel specification register (ADS) is started. When A/D conversion has been completed, the result of the A/D conversion is stored in the A/D conversion result register (ADCR), and an interrupt request signal (INTAD) is generated. Once the next A/D conversion has started and when one A/D conversion has been completed, the A/D conversion operation after that is immediately started. The A/D conversion operations are repeated until new data is written to ADS. If ADM, ADS, the power-fail comparison mode register (PFM), and the power-fail comparison threshold register (PFT) are rewritten during A/D conversion, the A/D conversion operation under execution is stopped and restarted from the beginning. If 0 is written to ADCS during A/D conversion, A/D conversion is immediately stopped. conversion result is undefined. Figure 10-10. A/D Conversion Operation Rewriting ADM ADCS = 1 At this time, the Rewriting ADS ADCS = 0 A/D conversion ANIn ANIn ANIn ANIm ANIm Conversion is stopped Conversion result is not retained Stopped ADCR ANIn ANIn ANIm INTAD (PFEN = 0) Remarks 1. n = 0 to 3 2. m = 0 to 3 192 User's Manual U15836EJ4V0UD CHAPTER 10 A/D CONVERTER (2) Power-fail detection function (when PFEN = 1) By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1 and bit 7 (PFEN) of the power-fail comparison mode register (PFM) to 1, the A/D conversion operation of the voltage applied to the analog input pin specified by the analog input channel specification register (ADS) is started. When the A/D conversion has been completed, the result of the A/D conversion is stored in the A/D conversion result register (ADCR), the values are compared with power-fail comparison threshold register (PFT), and an interrupt request signal (INTAD) is generated under the condition specified by bit 6 (PFCM) of PFM. <1> When PFEN = 1 and PFCM = 0 The higher 8 bits of ADCR and PFT values are compared when A/D conversion ends and INTAD is only generated when the higher 8 bits of ADCR PFT. <2> When PFEN = 1 and PFCM = 1 The higher 8 bits of ADCR and PFT values are compared when A/D conversion ends and INTAD is only generated when the higher 8 bits of ADCR < PFT. Figure 10-11. Power-Fail Detection (When PFEN = 1 and PFCM = 0) A/D conversion ANIn ANIn ANIn ANIn Higher 8 bits of ADCR 80H 7FH 80H PFT 80H INTAD (PFEN = 1) Note First conversion Condition match Note If the conversion result is not read before the end of the next conversion after INTAD is output, the result is replaced by the next conversion result. Remark n = 0 to 3 User's Manual U15836EJ4V0UD 193 CHAPTER 10 A/D CONVERTER The setting methods are described below. * When used as A/D conversion operation <1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1. <2> Select the channel and conversion time using bits 1 and 0 (ADS1 and ADS0) of the analog input channel specification register (ADS) and bits 5 to 3 (FR2 to FR0) of ADM. <3> Set bit 7 (ADCS) of ADM to 1. <4> An interrupt request signal (INTAD) is generated. <5> Transfer the A/D conversion data to the A/D conversion result register (ADCR). 194 User's Manual U15836EJ4V0UD CHAPTER 10 A/D CONVERTER 10.5 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit). The percentage of 1LSB with respect to the full scale is expressed by %FSR (Full Scale Range). 1LSB is as follows when the resolution is 10 bits. 1LSB = 1/210 = 1/1024 = 0.098%FSR Accuracy has no relation to resolution, but is determined by overall error. (2) Overall error This shows the maximum error value between the actual measured value and the theoretical value. Zero-scale error, full-scale error, integral linearity error, and differential linearity errors that are combinations of these express the overall error. Note that the quantization error is not included in the overall error in the characteristics table. (3) Quantization error When analog values are converted to digital values, a 1/2LSB error naturally occurs. In an A/D converter, an analog input voltage in a range of 1/2LSB is converted to the same digital code, so a quantization error cannot be avoided. Note that the quantization error is not included in the overall error, zero-scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. Figure 10-12. Overall Error 1......1 Figure 10-13. Quantization Error 1......1 Ideal line Digital output Overall error Digital output 1/2LSB Quantization error 1/2LSB 0......0 0 Analog input AVREF 0......0 0 Analog input AVREF User's Manual U15836EJ4V0UD 195 CHAPTER 10 A/D CONVERTER (4) Zero-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (1/2LSB) when the digital output changes from 0......000 to 0......001. If the actual measurement value is greater than the theoretical value, it shows the difference between the actual measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output changes from 0......001 to 0......010. (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (Full-scale - 3/2LSB) when the digital output changes from 1......110 to 1......111. (6) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0. (7) Differential linearity error While the ideal width of code output is 1LSB, this indicates the difference between the actual measurement value and the ideal value. Figure 10-14. Zero-Scale Error 111 Digital output (Lower 3 bits) Figure 10-15. Full-Scale Error Digital output (Lower 3 bits) Ideal line 011 Full-scale error 111 110 101 000 010 001 000 0 1 2 3 AVREF Analog input (LSB) Zero-scale error Ideal line 0 AVREF-3 AVREF-2 AVREF-1 AVREF Analog input (LSB) Figure 10-16. Integral Linearity Error Figure 10-17. Differential Linearity Error 1......1 1......1 Ideal line Digital output Ideal 1LSB width Digital output 0......0 0 Integral linearity error Analog input AVREF Differential linearity error 0......0 0 Analog input AVREF 196 User's Manual U15836EJ4V0UD CHAPTER 10 A/D CONVERTER (8) Conversion time This expresses the time since sampling has been started until digital output is obtained. The sampling time is included in the conversion time in the characteristics table. (9) Sampling time This is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit. Sampling time Conversion time 10.6 Cautions for A/D Converter (1) Operating current in standby mode The A/D converter stops operating in the standby mode. At this time, the operating current can be reduced by clearing bit 7 (ADCS) of the A/D converter mode register (ADM) to 0. Figure 10-18 shows the circuit configuration of the series resistor string. Figure 10-18. Circuit Configuration of Series Resistor String AVREF P-ch ADCS Series resistor string AVSS (2) Input range of ANI0 to ANI3 Observe the rated range of the ANI0 to ANI3 input voltage. If a voltage of AVREF or higher and AVSS or lower (even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that channel becomes undefined. In addition, the converted values of the other channels may also be affected. (3) Conflicting operations <1> Conflict between A/D conversion result register (ADCR) write and ADCR read by instruction upon the end of conversion ADCR read has priority. After the read operation, the new conversion result is written to ADCR. <2> Conflict between ADCR write and A/D converter mode register (ADM) write or analog input channel specification register (ADS) write upon the end of conversion ADM or ADS write has priority. ADCR write is not performed, nor is the conversion end interrupt signal (INTAD) generated. User's Manual U15836EJ4V0UD 197 CHAPTER 10 A/D CONVERTER (4) Noise countermeasures To maintain the 10-bit resolution, attention must be paid to noise input to the AVREF and ANI0 to ANI3 pins. Because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally, as shown in Figure 10-19, to reduce noise. Figure 10-19. Analog Input Pin Connection If there is a possibility that noise equal to or higher than AVREF or equal to or lower than AVSS may enter, clamp with a diode with a small VF value (0.3 V or lower). Reference voltage input AVREF ANI0 to ANI3 C = 100 to 1,000 pF AVSS VSS (5) ANI0/P20 to ANI3/P23 <1> The analog input pins (ANI0 to ANI3) are also used as input port pins (P20 to P23). When A/D conversion is performed with any of ANI0 to ANI3 selected, do not access port 2 while conversion is in progress; otherwise the conversion resolution may be degraded. <2> If a digital pulse is applied to the pins adjacent to the pins currently being used for A/D conversion, the expected value of the A/D conversion may not be obtained due to coupling noise. Therefore, do not apply a pulse to the pins adjacent to the pin undergoing A/D conversion. (6) Input impedance of ANI0 to ANI3 pins In this A/D converter, the internal sampling capacitor is charged and sampling is performed for approx. one sixth of the conversion time. Since only the leakage current flows other than during sampling and the current for charging the capacitor also flows during sampling, the input impedance fluctuates and has no meaning. To perform sufficient sampling, however, it is recommended to make the output impedance of the analog input source 10 k or lower, or attach a capacitor of around 100 pF to the ANI0 to ANI3 pins (see Figure 10-19). (7) AVREF pin input impedance A series resistor string of several tens of 10 k is connected between the AVREF and AVSS pins. Therefore, if the output impedance of the reference voltage source is high, this will result in a series connection to the series resistor string between the AVREF and AVSS pins, resulting in a large reference voltage error. 198 User's Manual U15836EJ4V0UD CHAPTER 10 A/D CONVERTER (8) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the pre-change analog input may be set just before the ADS rewrite. Caution is therefore required since, at this time, when ADIF is read immediately after the ADS rewrite, ADIF is set despite the fact A/D conversion for the postchange analog input has not finished. When A/D conversion is stopped and then resumed, clear ADIF before the A/D conversion operation is resumed. Figure 10-20. Timing of A/D Conversion End Interrupt Request Generation ADS rewrite (start of ANIn conversion) ADS rewrite (start of ANIm conversion) ADIF is set but ANIm conversion has not finished. A/D conversion ANIn ANIn ANIm ANIm ADCR ANIn ANIn ANIm ANIm INTAD Remarks 1. n = 0 to 3 2. m = 0 to 3 (9) Conversion results just after A/D conversion start The first A/D conversion value immediately after A/D conversion starts may not fall within the rating range if the ADCS bit is set to 1 within 14 s after the ADCE bit was set to 1, or if the ADCS bit is set to 1 with the ADCE bit = 0. Take measures such as polling the A/D conversion end interrupt request (INTAD) and removing the first conversion result. (10) A/D conversion result register (ADCR) read operation When a write operation is performed to the A/D converter mode register (ADM) and analog input channel specification register (ADS), the contents of ADCR may become undefined. Read the conversion result following conversion completion before writing to ADM and ADS. Using a timing other than the above may cause an incorrect conversion result to be read. User's Manual U15836EJ4V0UD 199 CHAPTER 10 A/D CONVERTER (11) A/D converter sampling time and A/D conversion start delay time The A/D converter sampling time differs depending on the set value of the A/D converter mode register (ADM). A delay time exists until actual sampling is started after A/D converter operation is enabled. When using a set in which the A/D conversion time must be strictly observed, care is required regarding the contents shown in Figure 10-21 and Table 10-3. Figure 10-21. Timing of A/D Converter Sampling and A/D Conversion Start Delay ADCS 1 or ADS rewrite ADCS Sampling timing INTAD Wait period A/D Sampling conversion time start delay time Sampling time Conversion time Conversion time Table 10-3. A/D Converter Sampling Time and A/D Conversion Start Delay Time (ADM Set Value) FR2 FR1 FR0 Conversion Time Sampling Time A/D Conversion Start Delay Time MIN. 0 0 0 1 1 1 0 0 1 0 0 1 Other than above 0 1 0 0 1 0 288/fX 240/fX 192/fX 144/fX 120/fX 96/fX Setting prohibited 40/fX 32/fX 24/fX 20/fX 16/fX 12/fX - 32/fX 28/fX 24/fX 16/fX 14/fX 12/fX - 36/fX 32/fX 28/fX 18/fX 16/fX 14/fX - MAX. Note Note The A/D conversion start delay time is the time after the wait period. For the wait function, see CHAPTER 28 CAUTIONS FOR WAIT. Remark fX: X1 clock oscillation frequency 200 User's Manual U15836EJ4V0UD CHAPTER 10 A/D CONVERTER (12) Internal equivalent circuit The equivalent circuit of the analog input block is shown below. Figure 10-22. Internal Equivalent Circuit of ANIn Pin R1 ANIn C1 C2 C3 R2 Table 10-4. Resistance and Capacitance Values of Equivalent Circuit (Reference Values) AVREF 2.7 V 4.5 V R1 12 k 4 k R2 8 k 2.7 k C1 8 pF 8 pF C2 3 pF 1.4 pF C3 2 pF 2 pF Remarks 1. The resistance and capacitance values shown in Table 10-4 are not guaranteed values. 2. n = 0 to 3 User's Manual U15836EJ4V0UD 201 CHAPTER 11 SERIAL INTERFACE UART0 (PD780102, 780103, 78F0103 ONLY) 11.1 Functions of Serial Interface UART0 Serial interface UART0 has the following two modes. (1) Operation stop mode This mode is used when serial communication is not executed and can enable a reduction in the power consumption. For details, see 11.4.1 Operation stop mode. (2) Asynchronous serial interface (UART) mode The functions of this mode are outlined below. For details, see 11.4.2 generator. * Two-pin configuration TXD0: Transmit data output pin RXB0: Receive data input pin * Length of communication data can be selected from 7 or 8 bits. * Dedicated on-chip 5-bit baud rate generator allowing any baud rate to be set * Transmission and reception can be performed independently. * Four operating clock inputs selectable * Fixed to LSB-first communication Cautions 1. If clock supply to serial interface UART0 is not stopped (e.g., in the HALT mode), normal operation continues. If clock supply to serial interface UART0 is stopped (e.g., in the STOP mode), each register stops operating, and holds the value immediately before clock supply was stopped. The TXD0 pin also holds the value immediately before clock supply was stopped and outputs it. However, the operation is not guaranteed after clock supply is resumed. Therefore, reset the circuit so that POWER0 = 0, RXE0 = 0, and TXE0 = 0. 2. Set POWER0 = 1 and then set TXE0 = 1 (transmission) or RXE0 = 1 (reception) to start communication. 3. TXE0 and RXE0 are synchronized by the base clock (fXCLK0) set by BRGC0. To enable transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks of base clock after TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set within two clocks of base clock, the transmission circuit or reception circuit may not be initialized. Asynchronous serial interface (UART) mode and 11.4.3 Dedicated baud rate 202 User's Manual U15836EJ4V0UD CHAPTER 11 SERIAL INTERFACE UART0 (PD780102, 780103, 78F0103 ONLY) 11.2 Configuration of Serial Interface UART0 Serial interface UART0 includes the following hardware. Table 11-1. Configuration of Serial Interface UART0 Item Registers Receive buffer register 0 (RXB0) Receive shift register 0 (RXS0) Transmit shift register 0 (TXS0) Control registers Asynchronous serial interface operation mode register 0 (ASIM0) Asynchronous serial interface reception error status register 0 (ASIS0) Baud rate generator control register 0 (BRGC0) Port mode register 1 (PM1) Port register 1 (P1) Configuration User's Manual U15836EJ4V0UD 203 fX/25 Selector 204 fX/2 fX/23 Asynchronous serial interface operation mode register 0 (ASIM0) Figure 11-1. Block Diagram of Serial Interface UART0 Filter RxD0/ SI10/P11 CHAPTER 11 SERIAL INTERFACE UART0 (PD780102, 780103, 78F0103 ONLY) Receive shift register 0 (RXS0) Asynchronous serial interface reception error status register 0 (ASIS0) Baud rate generator Reception unit Internal bus INTSR0 Reception control Receive buffer register 0 (RXB0) User's Manual U15836EJ4V0UD 8-bit timer/ event counter 50 output Baud rate generator control register 0 (BRGC0) 7 7 Baud rate generator INTST0 Transmission control Transmit shift register 0 (TXS0) Output latch (P10) PM10 TxD0/ SCK10/P10 Registers Transmission unit CHAPTER 11 SERIAL INTERFACE UART0 (PD780102, 780103, 78F0103 ONLY) (1) Receive buffer register 0 (RXB0) This 8-bit register stores parallel data converted by receive shift register 0 (RXS0). Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register 0 (RXS0). If the data length is set to 7 bits the receive data is transferred to bits 0 to 6 of RXB0 and the MSB of RXB0 is always 0. If an overrun error (OVE0) occurs, the receive data is not transferred to RXB0. RXB0 can be read by an 8-bit memory manipulation instruction. No data can be written to this register. RESET input or POWER0 = 0 sets this register to FFH. (2) Receive shift register 0 (RXS0) This register converts the serial data input to the RXD0 pin into parallel data. RXS0 cannot be directly manipulated by a program. (3) Transmit shift register 0 (TXS0) This register is used to set transmit data. Transmission is started when data is written to TXS0, and serial data is transmitted from the TXD0 pin. TXS0 can be written by an 8-bit memory manipulation instruction. This register cannot be read. RESET input, POWER0 = 0, or TXE0 = 0 sets this register to FFH. Caution Do not write the next transmit data to TXS0 before the transmission completion interrupt signal (INTST0) is generated. User's Manual U15836EJ4V0UD 205 CHAPTER 11 SERIAL INTERFACE UART0 (PD780102, 780103, 78F0103 ONLY) 11.3 Registers Controlling Serial Interface UART0 Serial interface UART0 is controlled by the following five registers. * Asynchronous serial interface operation mode register 0 (ASIM0) * Asynchronous serial interface reception error status register 0 (ASIS0) * Baud rate generator control register 0 (BRGC0) * Port mode register 1 (PM1) * Port register 1 (P1) (1) Asynchronous serial interface operation mode register 0 (ASIM0) This 8-bit register controls the serial communication operations of serial interface UART0. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 01H. Figure 11-2. Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) (1/2) Address: FF70H After reset: 01H R/W Symbol ASIM0 <7> POWER0 <6> TXE0 <5> RXE0 4 PS01 3 PS00 2 CL0 1 SL0 0 1 POWER0 0 Note 1 Enables/disables operation of internal operation clock Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit Note 2 . 1 Enables operation of the internal operation clock. TXE0 0 1 Enables/disables transmission Disables transmission (synchronously resets the transmission circuit). Enables transmission. RXE0 0 1 Enables/disables reception Disables reception (synchronously resets the reception circuit). Enables reception. Notes 1. 2. The input from the RXD0 pin is fixed to high level when POWER0 = 0. Asynchronous serial interface reception error status register 0 (ASIS0), transmit shift register 0 (TXS0), and receive buffer register 0 (RXB0) are reset. 206 User's Manual U15836EJ4V0UD CHAPTER 11 SERIAL INTERFACE UART0 (PD780102, 780103, 78F0103 ONLY) Figure 11-2. Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) (2/2) PS01 0 0 1 1 PS00 0 1 0 1 Transmission operation Does not output parity bit. Outputs 0 parity. Outputs odd parity. Outputs even parity. Reception operation Reception without parity Reception as 0 parity Note Judges as odd parity. Judges as even parity. CL0 0 1 Specifies character length of transmit/receive data Character length of data = 7 bits Character length of data = 8 bits SL0 0 1 Number of stop bits = 1 Number of stop bits = 2 Specifies number of stop bits of transmit data Note If "reception as 0 parity" is selected, the parity is not judged. Therefore, bit 2 (PE0) of asynchronous serial interface reception error status register 0 (ASIS0) is not set and the error interrupt does not occur. Cautions 1. At startup, set POWER0 to 1 and then set TXE0 to 1. To stop the operation, clear TXE0 to 0, and then clear POWER0 to 0. 2. At startup, set POWER0 to 1 and then set RXE0 to 1. To stop the operation, clear RXE0 to 0, and then clear POWER0 to 0. 3. Set POWER0 to 1 and then set RXE0 to 1 while a high level is input to the RxD0 pin. If POWER0 is set to 1 and RXE0 is set to 1 while a low level is input, reception is started. 4. TXE0 and RXE0 are synchronized by the base clock (fXCLK0) set by BRGC0. To enable transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks of base clock after TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set within two clocks of base clock, the transmission circuit or reception circuit may not be initialized. 5. Clear the TXE0 and RXE0 bits to 0 before rewriting the PS01, PS00, and CL0 bits. 6. Make sure that TXE0 = 0 when rewriting the SL0 bit. Reception is always performed with "number of stop bits = 1", and therefore, is not affected by the set value of the SL0 bit. 7. Be sure to set bit 0 to 1. User's Manual U15836EJ4V0UD 207 CHAPTER 11 SERIAL INTERFACE UART0 (PD780102, 780103, 78F0103 ONLY) (2) Asynchronous serial interface reception error status register 0 (ASIS0) This register indicates an error status on completion of reception by serial interface UART0. It includes three error flag bits (PE0, FE0, OVE0). This register is read-only by an 8-bit memory manipulation instruction. RESET input clears this register to 00H if bit 7 (POWER0) and bit 5 (RXE0) of ASIM0 = 0. 00H is read when this register is read. Figure 11-3. Format of Asynchronous Serial Interface Reception Error Status Register 0 (ASIS0) Address: FF73H After reset: 00H R Symbol ASIS0 7 0 6 0 5 0 4 0 3 0 2 PE0 1 FE0 0 OVE0 PE0 0 1 Status flag indicating parity error If POWER0 = 0 and RXE0 = 0, or if the ASIS0 register is read. If the parity of transmit data does not match the parity bit on completion of reception. FE0 0 1 Status flag indicating framing error If POWER0 = 0 and RXE0 = 0, or if the ASIS0 register is read. If the stop bit is not detected on completion of reception. OVE0 0 1 Status flag indicating overrun error If POWER0 = 0 and RXE0 = 0, or if the ASIS0 register is read. If receive data is set to the RXB register and the next reception operation is completed before the data is read. Cautions 1. The operation of the PE0 bit differs depending on the set values of the PS01 and PS00 bits of asynchronous serial interface operation mode register 0 (ASIM0). 2. Only the first bit of the receive data is checked as the stop bit, regardless of the number of stop bits. 3. If an overrun error occurs, the next receive data is not written to receive buffer register 0 (RXB0) but discarded. 4. If data is read from ASIS0, a wait cycle is generated. For details, see CHAPTER 28 CAUTIONS FOR WAIT. 208 User's Manual U15836EJ4V0UD CHAPTER 11 SERIAL INTERFACE UART0 (PD780102, 780103, 78F0103 ONLY) (3) Baud rate generator control register 0 (BRGC0) This register selects the base clock of serial interface UART0 and the division value of the 5-bit counter. BRGC0 can be set by an 8-bit memory manipulation instruction. RESET input sets this register to 1FH. Figure 11-4. Format of Baud Rate Generator Control Register 0 (BRGC0) Address: FF71H After reset: 1FH R/W Symbol BRGC0 7 TPS01 6 TPS00 5 0 4 MDL04 3 MDL03 2 MDL02 1 MDL01 0 MDL00 TPS01 0 0 1 1 TPS00 0 1 0 1 TM50 output fX/2 (5 MHz) fX/2 (1.25 MHz) fX/2 (312.5 kHz) 5 3 Note Base clock (fXCLK0) selection MDL04 MDL03 MDL02 x 0 0 0 * * * * * 0 0 1 1 1 MDL01 x 0 0 1 * * * * * 1 1 0 1 1 MDL00 x 0 1 0 * * * * * 0 1 0 0 1 k x 8 9 10 * * * * * 26 27 28 30 31 Selection of 5-bit counter output clock 0 0 0 0 * * * * * 1 1 1 1 1 0 1 1 1 * * * * * 1 1 1 1 1 Setting prohibited fXCLK0/8 fXCLK0/9 fXCLK0/10 * * * * * fXCLK0/26 fXCLK0/27 fXCLK0/28 fXCLK0/30 fXCLK0/31 Note To select the TM50 output as the base clock, start an operation by setting 8-bit timer/event counter 50 so that the duty is 50% of the output in the PWM mode (bit 6 (TMC506) of the TMC50 register = 1), and then clear TPS01 and TPS00 to 0. It is not necessary to enable the TO50 pin as a timer output pin (bit 0 (TOE50) of the TMC register may be 0 or 1). Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the Ring-OSC oscillator is divided and supplied as the count clock. If the base clock is the RingOSC clock, the operation of serial interface UART0 is not guaranteed. 2. Make sure that bit 6 (TXE0) and bit 5 (RXE0) of the ASIM0 register = 0 when rewriting the MDL04 to MDL00 bits. 3. The baud rate value is the output clock of the 5-bit counter divided by 2. User's Manual U15836EJ4V0UD 209 CHAPTER 11 SERIAL INTERFACE UART0 (PD780102, 780103, 78F0103 ONLY) Remarks 1. fXCLK0: Frequency of base clock selected by the TPS01 and TPS00 bits 2. fX: 3. k: 4. x: X1 input clock oscillation frequency Value set by the MDL04 to MDL00 bits (k = 8, 9, 10, ..., 31) Don't care 5. Figures in parentheses apply to operation at fX = 10 MHz (4) Port mode register 1 (PM1) This register sets port 1 input/output in 1-bit units. When using the P10/TxD0/SCK10 pin for serial interface data output, clear PM10 to 0 and set the output latch of P10 to 1. Set PM11 to 1 when using the P11/RxD0/SI10 pin as a serial interface data input pin. The output latch of P11 at this time may be 0 or 1. PM1 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to FFH. Figure 11-5. Format of Port Mode Register 1 (PM1) Address: FF21H Symbol PM1 7 PM17 After reset: FFH 6 PM16 R/W 5 PM15 4 PM14 3 PM13 2 PM12 1 PM11 0 PM10 PM1n 0 1 P1n pin I/O mode selection (n = 0 to 7) Output mode (output buffer on) Input mode (output buffer off) 210 User's Manual U15836EJ4V0UD CHAPTER 11 SERIAL INTERFACE UART0 (PD780102, 780103, 78F0103 ONLY) 11.4 Operation of Serial Interface UART0 Serial interface UART0 has the following two modes. * Operation stop mode * Asynchronous serial interface (UART) mode 11.4.1 Operation stop mode In this mode, serial communication cannot be executed, thus reducing the power consumption. In addition, the pins can be used as ordinary port pins in this mode. To set the operation stop mode, clear bits 7, 6, and 5 (POWER0, TXE0, and RXE0) of ASIM0 to 0. (1) Register used The operation stop mode is set by asynchronous serial interface operation mode register 0 (ASIM0). ASIM0 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 01H. Address: FF70H After reset: 01H R/W Symbol ASIM0 <7> POWER0 <6> TXE0 <5> RXE0 4 PS01 3 PS00 2 CL0 1 SL0 0 1 POWER0 0 Note 1 Enables/disables operation of internal operation clock Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit Note 2 . TXE0 0 Enables/disables transmission Disables transmission (synchronously resets the transmission circuit). RXE0 0 Enables/disables reception Disables reception (synchronously resets the reception circuit). Notes 1. 2. The input from the RXD0 pin is fixed to high level when POWER0 = 0. Asynchronous serial interface reception error status register 0 (ASIS0), transmit shift register 0 (TXS0), and receive buffer register 0 (RXB0) are reset. Caution Clear POWER0 to 0 after clearing TXE0 and RXE0 to 0 to set the operation stop mode. To start the operation, set POWER0 to 1, and then set TXE0 and RXE0 to 1. Remark To use the RxD0/SI10/P11 and TxD0/SCK10/P10 pins as general-purpose port pins, see CHAPTER 4 PORT FUNCTIONS. User's Manual U15836EJ4V0UD 211 CHAPTER 11 SERIAL INTERFACE UART0 (PD780102, 780103, 78F0103 ONLY) 11.4.2 Asynchronous serial interface (UART) mode In this mode, 1-byte data is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates. (1) Registers used * Asynchronous serial interface operation mode register 0 (ASIM0) * Asynchronous serial interface reception error status register 0 (ASIS0) * Baud rate generator control register 0 (BRGC0) * Port mode register 1 (PM1) * Port register 1 (P1) The basic procedure of setting an operation in the UART mode is as follows. <1> Set the BRGC0 register (see Figure 11-4). <2> Set bits 1 to 4 (SL0, CL0, PS00, and PS01) of the ASIM0 register (see Figure 11-2). <3> Set bit 7 (POWER0) of the ASIM0 register to 1. <4> Set bit 6 (TXE0) of the ASIM0 register to 1. Transmission is enabled. Set bit 5 (RXE0) of the ASIM0 register to 1. Reception is enabled. <5> Write data to the TXS0 register. Data transmission is started. Caution Take relationship with the other party of communication when setting the port mode register and port register. The relationship between the register settings and pins is shown below. Table 11-2. Relationship Between Register Settings and Pins POWER0 TXE0 RXE0 PM10 P10 PM11 P11 UART0 Operation 0 1 0 0 1 1 0 1 0 1 x x Note Pin Function TxD0/SCK10/P10 SCK10/P10 SCK10/P10 TxD0 TxD0 RxD0/SI10/P11 SI10/P11 RxD0 SI10/P11 RxD0 x x Note x Note x Note Stop Reception Transmission Transmission/ reception Note Note 1 x Note x x Note 0 0 1 1 1 x Note Can be set as port function. Remark x: TXE0: RXE0: PM1x: P1x: don't care Bit 6 of ASIM0 Bit 5 of ASIM0 Port mode register Port output latch POWER0: Bit 7 of asynchronous serial interface operation mode register 0 (ASIM0) 212 User's Manual U15836EJ4V0UD CHAPTER 11 SERIAL INTERFACE UART0 (PD780102, 780103, 78F0103 ONLY) (2) Communication operation (a) Format and waveform example of normal transmit/receive data Figures 11-6 and 11-7 show the format and waveform example of the normal transmit/receive data. Figure 11-6. Format of Normal UART Transmit/Receive Data 1 data frame Start bit D0 D1 D2 D3 D4 D5 D6 D7 Parity bit Stop bit Character bits One data frame consists of the following bits. * Start bit ... 1 bit * Character bits ... 7 or 8 bits (LSB first) * Parity bit ... Even parity, odd parity, 0 parity, or no parity * Stop bit ... 1 or 2 bits The character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial interface operation mode register 0 (ASIM0). Figure 11-7. Example of Normal UART Transmit/Receive Data Waveform 1. Data length: 8 bits, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop 2. Data length: 7 bits, Parity: Odd parity, Stop bit: 2 bits, Communication data: 36H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 Parity Stop Stop 3. Data length: 8 bits, Parity: None, Stop bit: 1 bit, Communication data: 87H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 D7 Stop User's Manual U15836EJ4V0UD 213 CHAPTER 11 SERIAL INTERFACE UART0 (PD780102, 780103, 78F0103 ONLY) (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected. With zero parity and no parity, an error cannot be detected. (i) Even parity * Transmission Transmit data, including the parity bit, is controlled so that the number of bits that are "1" is even. The value of the parity bit is as follows. If transmit data has an odd number of bits that are "1": 1 If transmit data has an even number of bits that are "1": 0 * Reception The number of bits that are "1" in the receive data, including the parity bit, is counted. If it is odd, a parity error occurs. (ii) Odd parity * Transmission Unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that are "1" is odd. If transmit data has an odd number of bits that are "1": 0 If transmit data has an even number of bits that are "1": 1 * Reception The number of bits that are "1" in the receive data, including the parity bit, is counted. If it is even, a parity error occurs. (iii) 0 parity The parity bit is cleared to 0 when data is transmitted, regardless of the transmit data. The parity bit is not detected when the data is received. Therefore, a parity error does not occur regardless of whether the parity bit is "0" or "1". (iv) No parity No parity bit is appended to the transmit data. Reception is performed assuming that there is no parity bit when data is received. Because there is no parity bit, a parity error does not occur. 214 User's Manual U15836EJ4V0UD CHAPTER 11 SERIAL INTERFACE UART0 (PD780102, 780103, 78F0103 ONLY) (c) Transmission The TXD0 pin outputs a high level when bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is set to 1. If bit 6 (TXE0) of ASIM0 is then set to 1, transmission is enabled. Transmission can be started by writing transmit data to transmit shift register 0 (TXS0). The start bit, parity bit, and stop bit are automatically appended to the data. When transmission is started, the start bit is output from the TXD0 pin, followed by the rest of the data in order starting from the LSB. When transmission is completed, the parity and stop bits set by ASIM0 are appended and a transmission completion interrupt request (INTST0) is generated. Transmission is stopped until the data to be transmitted next is written to TXS0. Figure 11-8 shows the timing of the transmission completion interrupt request (INTST0). This interrupt occurs as soon as the last stop bit has been output. Caution After transmit data is written to TXS0, do not write the next transmit data before the transmission completion interrupt signal (INTST0) is generated. Figure 11-8. Transmission Completion Interrupt Request Timing 1. Stop bit length: 1 TXD0 (output) Start D0 D1 D2 D6 D7 Parity Stop INTST0 2. Stop bit length: 2 TXD0 (output) Start D0 D1 D2 D6 D7 Parity Stop INTST0 User's Manual U15836EJ4V0UD 215 CHAPTER 11 SERIAL INTERFACE UART0 (PD780102, 780103, 78F0103 ONLY) (d) Reception Reception is enabled and the RXD0 pin input is sampled when bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is set to 1 and then bit 5 (RXE0) of ASIM0 is set to 1. The 5-bit counter of the baud rate generator starts counting when the falling edge of the RXD0 pin input is detected. When the set value of baud rate generator control register 0 (BRGC0) has been counted, the RXD0 pin input is sampled again ( as a start bit. When the start bit is detected, reception is started, and serial data is sequentially stored in receive shift register 0 (RXS0) at the set baud rate. When the stop bit has been received, the reception completion interrupt (INTSR0) is generated and the data of RXS0 is written to receive buffer register 0 (RXB0). If an overrun error (OVE0) occurs, however, the receive data is not written to RXB0. Even if a parity error (PE0) occurs while reception is in progress, reception continues to the reception position of the stop bit, and an error interrupt (INTSR0) is generated after completion of reception. Figure 11-9. Reception Completion Interrupt Request Timing in Figure 11-9). If the RXD0 pin is low level at this time, it is recognized RXD0 (input) Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop INTSR0 RXB0 Cautions 1. Be sure to read receive buffer register 0 (RXB0) even if a reception error occurs. Otherwise, an overrun error will occur when the next data is received, and the reception error status will persist. 2. Reception is always performed with the "number of stop bits = 1". The second stop bit is ignored. 3. Be sure to read asynchronous serial interface reception error status register 0 (ASIS0) before reading RXB0. 216 User's Manual U15836EJ4V0UD CHAPTER 11 SERIAL INTERFACE UART0 (PD780102, 780103, 78F0103 ONLY) (e) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 0 (ASIS0) is set as a result of data reception, a reception error interrupt request (INTSR0) is generated. Which error has occurred during reception can be identified by reading the contents of ASIS0 in the reception error interrupt servicing (INTSR0) (see Figure 11-3). The contents of ASIS0 are reset to 0 when ASIS0 is read. Table 11-3. Cause of Reception Error Reception Error Parity error Cause The parity specified for transmission does not match the parity of the receive data. Framing error Overrun error Stop bit is not detected. Reception of the next data is completed before data is read from receive buffer register 0 (RXB0). (f) Noise filter of receive data The RXD0 signal is sampled using the base clock output by the prescaler block. If two sampled values are the same, the output of the match detector changes, and the data is sampled as input data. Because the circuit is configured as shown in Figure 11-10, the internal processing of the reception operation is delayed by two clocks from the external signal status. Figure 11-10. Noise Filter Circuit Base clock RXD0/SI10/P11 In Q Internal signal A In Q Internal signal B Match detector LD_EN User's Manual U15836EJ4V0UD 217 CHAPTER 11 SERIAL INTERFACE UART0 (PD780102, 780103, 78F0103 ONLY) 11.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and a 5-bit programmable counter, and generates a serial clock for transmission/reception of UART0. Separate 5-bit counters are provided for transmission and reception. (1) Configuration of baud rate generator * Base clock The clock selected by bits 7 and 6 (TPS01 and TPS00) of baud rate generator control register 0 (BRGC0) is supplied to each module when bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is 1. This clock is called the base clock and its frequency is called fXCLK0. The base clock is fixed to low level when POWER0 = 0. * Transmission counter This counter stops, cleared to 0, when bit 7 (POWER0) or bit 6 (TXE0) of asynchronous serial interface operation mode register 0 (ASIM0) is 0. It starts counting when POWER0 = 1 and TXE0 = 1. The counter is cleared to 0 when the first data transmitted is written to transmit shift register 0 (TXS0). * Reception counter This counter stops operation, cleared to 0, when bit 7 (POWER0) or bit 5 (RXE0) of asynchronous serial interface operation mode register 0 (ASIM0) is 0. It starts counting when the start bit has been detected. The counter stops operation after one frame has been received, until the next start bit is detected. Figure 11-11. Configuration of Baud Rate Generator POWER0 Baud rate generator fX/2 POWER0, TXE0 (or RXE0) fX/23 Selector fX/25 8-bit timer/ event counter 50 output fXCLK0 5-bit counter Match detector 1/2 Baud rate BRGC0: TPS01, TPS00 BRGC0: MDL04 to MDL00 Remark POWER0: Bit 7 of asynchronous serial interface operation mode register 0 (ASIM0) TXE0: RXE0: BRGC0: Bit 6 of ASIM0 Bit 5 of ASIM0 Baud rate generator control register 0 User's Manual U15836EJ4V0UD 218 CHAPTER 11 SERIAL INTERFACE UART0 (PD780102, 780103, 78F0103 ONLY) (2) Generation of serial clock A serial clock can be generated by using baud rate generator control register 0 (BRGC0). Select the clock to be input to the 5-bit counter by using bits 7 and 6 (TPS01 and TPS00) of BRGC0. Bits 4 to 0 (MDL04 to MDL00) of BRGC0 can be used to select the division value of the 5-bit counter. (a) Baud rate The baud rate can be calculated by the following expression. * Baud rate = fXCLK0: k: fXCLK0 2xk [bps] Frequency of base clock selected by the TPS01 and TPS00 bits of the BRGC0 register Value set by the MDL04 to MDL00 bits of the BRGC0 register (k = 8, 9, 10, ..., 31) (b) Error of baud rate The baud rate error can be calculated by the following expression. * Error (%) = Actual baud rate (baud rate with error) Desired baud rate (correct baud rate) - 1 x 100 [%] Cautions 1. Keep the baud rate error during transmission to within the permissible error range at the reception destination. 2. Make sure that the baud rate error during reception satisfies the range shown in (4) Permissible baud rate range during reception. Example: Frequency of base clock = 2.5 MHz = 2,500,000 Hz Set value of MDL04 to MDL00 bits of BRGC0 register = 10000B (k = 16) Target baud rate = 76,800 bps Baud rate = 2.5 M/(2 x 16) = 2,500,000/(2 x 16) = 78125 [bps] Error = (78,125/76,800 - 1) x 100 = 1.725 [%] User's Manual U15836EJ4V0UD 219 CHAPTER 11 SERIAL INTERFACE UART0 (PD780102, 780103, 78F0103 ONLY) (3) Example of setting baud rate Table 11-4. Set Data of Baud Rate Generator Baud Rate [bps] TPS01, TPS00 2400 4800 9600 10400 19200 31250 38400 76800 115200 153600 230400 - - 3 3 3 2 2 2 1 1 1 - - 16 15 8 20 16 8 22 16 11 fX = 10.0 MHz k Calculated ERR[%] Value - - 9766 10417 19531 31250 39063 78125 113636 156250 227273 - - 1.73 0.16 1.73 0 1.73 1.73 -1.36 1.73 -1.36 TPS01, TPS00 - 3 3 3 2 2 2 1 1 1 1 - 27 14 13 27 17 14 27 18 14 9 fX = 8.38 MHz k Calculated ERR[%] Value - 4850 9353 10072 19398 30809 38796 77593 116389 149643 232778 - 1.03 -2.58 -3.15 1.03 -1.41 -2.58 1.03 1.03 -2.58 1.03 TPS01, TPS00 3 3 2 2 2 - 2 1 1 - - 27 14 27 25 14 - 27 14 9 - - fX = 4.19 MHz k Calculated ERR[%] Value 2425 4676 9699 10475 18705 - 38796 74821 116389 - - 1.03 -2.58 1.03 0.72 -2.58 - 1.03 -2.58 1.03 - - Remark TPS01, TPS00: Bits 7 and 6 of baud rate generator control register 0 (BRGC0) (setting of base clock (fXCLK0)) k: fX: ERR: Value set by the MDL04 to MDL00 bits of BRGC0 (k = 8, 9, 10, ..., 31) X1 input clock oscillation frequency Baud rate error 220 User's Manual U15836EJ4V0UD CHAPTER 11 SERIAL INTERFACE UART0 (PD780102, 780103, 78F0103 ONLY) (4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below. Figure 11-12. Permissible Baud Rate Range During Reception Latch timing Data frame length of UART0 Start bit Bit 0 FL Bit 1 Bit 7 Parity bit Stop bit 1 data frame (11 x FL) Minimum permissible data frame length Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmin Maximum permissible data frame length Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmax As shown in Figure 11-12, the latch timing of the receive data is determined by the counter set by baud rate generator control register 0 (BRGC0) after the start bit has been detected. If the last data (stop bit) meets this latch timing, the data can be correctly received. Assuming that 11-bit data is received, the theoretical values can be calculated as follows. FL = (Brate)-1 Brate: Baud rate of UART0 k: FL: Set value of BRGC0 1-bit data length Margin of latch timing: 2 clocks User's Manual U15836EJ4V0UD 221 CHAPTER 11 SERIAL INTERFACE UART0 (PD780102, 780103, 78F0103 ONLY) Minimum permissible data frame length: FLmin = 11 x FL - k-2 2k x FL = 21k + 2 2k FL Therefore, the maximum receivable baud rate at the transmission destination is as follows. BRmax = (FLmin/11)-1 = 22k 21k + 2 Brate Similarly, the maximum permissible data frame length can be calculated as follows. 10 11 x FLmax = 11 x FL - 21k - 2 20k k+2 2xk x FL = 21k - 2 2xk FL FLmax = FL x 11 Therefore, the minimum receivable baud rate at the transmission destination is as follows. BRmin = (FLmax/11)-1 = 20k 21k - 2 Brate The permissible baud rate error between UART0 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions, as follows. Table 11-5. Maximum/Minimum Permissible Baud Rate Error Division Ratio (k) 8 16 24 31 Maximum Permissible Baud Rate Error +3.53% +4.14% +4.34% +4.44% Minimum Permissible Baud Rate Error -3.61% -4.19% -4.38% -4.47% Remarks 1. The permissible reception error depends on the number of bits in one frame, input clock frequency, and division ratio (k). The higher the input clock frequency and the higher the division ratio (k), the higher the permissible reception error. 2. k: Set value of BRGC0 222 User's Manual U15836EJ4V0UD CHAPTER 12 SERIAL INTERFACE UART6 12.1 Functions of Serial Interface UART6 Serial interface UART6 has the following two modes. (1) Operation stop mode This mode is used when serial communication is not executed and can enable a reduction in the power consumption. For details, see 12.4.1 Operation stop mode. (2) Asynchronous serial interface (UART) mode This mode supports the LIN (Local Interconnect Network)-bus. The functions of this mode are outlined below. For details, see 12.4.2 generator. * Two-pin configuration TXD6: Transmit data output pin RXB6: Receive data input pin * Data length of communication data can be selected from 7 or 8 bits. * Dedicated internal 8-bit baud rate generator allowing any baud rate to be set * Transmission and reception can be performed independently. * Twelve operating clock inputs selectable * MSB- or LSB-first communication selectable * Inverted transmission operation * Synchronous break field transmission from 13 to 20 bits * More than 11 bits can be identified for synchronous break field reception (SBF reception flag provided). Cautions 1. The TXD6 output inversion function inverts only the transmission side and not the reception side. To use this function, the reception side must be ready for reception of inverted data. 2. If clock supply to serial interface UART6 is not stopped (e.g., in the HALT mode), normal operation continues. If clock supply to serial interface UART6 is stopped (e.g., in the STOP mode), each register stops operating, and holds the value immediately before clock supply was stopped. The TXD6 pin also holds the value immediately before clock supply was stopped and outputs it. However, the operation is not guaranteed after clock supply is resumed. Therefore, reset the circuit so that POWER6 = 0, RXE6 = 0, and TXE6 = 0. 3. If data is continuously transmitted, the communication timing from the stop bit to the next start bit is extended two operating clocks of the macro. However, this does not affect the result of communication because the reception side initializes the timing when it has detected a start bit. Do not use the continuous transmission function if the interface is incorporated in LIN. Asynchronous serial interface (UART) mode and 12.4.3 Dedicated baud rate User's Manual U15836EJ4V0UD 223 CHAPTER 12 SERIAL INTERFACE UART6 Remark LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network. LIN communication is single-master communication, and up to 15 slaves can be connected to one master. The LIN slaves are used to control the switches, actuators, and sensors, and these are connected to the LIN master via the LIN network. Normally, the LIN master is connected to a network such as CAN (Controller Area Network). In addition, the LIN bus uses a single-wire method and is connected to the nodes via a transceiver that complies with ISO9141. In the LIN protocol, the master transmits a frame with baud rate information and the slave receives it and corrects the baud rate error. Therefore, communication is possible when the baud rate error in the slave is 15% or less. Figures 12-1 and 12-2 outline the transmission and reception operations of LIN. Figure 12-1. LIN Transmission Operation Wakeup signal frame Synchronous break field Synchronous field Indent field Data field Data field Checksum field Sleep bus 8 bits Note 1 13-bitNote 2 SBF transmission 55H Data Data Data Data transmission transmission transmission transmission transmission TX6 Note 3 INTST6 Notes 1. 2. 3. Remark The wakeup signal frame is substituted by 80H transmission in the 8-bit mode. The synchronous break field is output by hardware. The output width is adjusted by baud rate generator control register 6 (BRGC6) (see 12.4.2 (2) (h) SBF transmission). INTST6 is output on completion of each transmission. It is also output when SBF is transmitted. The interval between each field is controlled by software. 224 User's Manual U15836EJ4V0UD CHAPTER 12 SERIAL INTERFACE UART6 Figure 12-2. LIN Reception Operation Wakeup signal frame Sleep bus 13 bitsNote 2 SBF reception Note 3 Reception interrupt (INTSR6) SF reception ID reception Data reception Data Data reception receptionNote 5 Synchronous break field Synchronous field Indent field Data field Data field Checksum field RX6 Disable Enable Edge detection Note 1 (INTP0) Note 4 Capture timer Disable Enable Notes 1. 2. The wakeup signal is detected at the edge of the pin, and enables UART6 and sets the SBF reception mode. Reception continues until the STOP bit is detected. When an SBF with low-level data of 11 bits or more has been detected, it is assumed that SBF reception has been completed correctly, and an interrupt signal is output. If an SBF with low-level data of less than 11 bits has been detected, it is assumed that an SBF reception error has occurred. The interrupt signal is not output and the SBF reception mode is restored. 3. If SBF reception has been completed correctly, an interrupt signal is output. This SBF reception completion interrupt enables the capture timer. Detection of errors OVE6, PE6, and FE6 is suppressed, and error detection processing of UART communication and data transfer of the shift register and RXB6 is not performed. The shift register holds the reset value FFH. 4. 5. Calculate the baud rate error from the bit length of the synchronous field, disable UART6 after SF reception, and then re-set baud rate generator control register 6 (BRGC6). Distinguish the checksum field by software. Also perform processing by software to initialize UART6 after reception of the checksum field and to set the SBF reception mode again. To perform a LIN receive operation, use a configuration like the one shown in Figure 12-3. The wakeup signal transmitted from the LIN master is received by detecting the edge of the external interrupt (INTP0). The length of the synchronous field transmitted from the LIN master can be measured using the external event capture operation of 16-bit timer/event counter 00, and the baud rate error can be calculated. The input signal of the reception port input (RxD6) can be input to the external interrupt (INTP0) and 16-bit timer/event counter 00 by port input switch control (ISC0/ISC1), without connecting RxD6 and INTP0/TI000 externally. User's Manual U15836EJ4V0UD 225 CHAPTER 12 SERIAL INTERFACE UART6 Figure 12-3. Port Configuration for LIN Reception Operation Selector P14/RxD6 RXD6 input Port mode (PM14) Output latch (P14) Selector Selector P120/INTP0 INTP0 input Port mode (PM120) Output latch (P120) Port input switch control (ISC0) Selector P00/TI000 TI000 input Port mode (PM00) Output latch (P00) Port input switch control (ISC1) Remark ISC0, ISC1: Bits 0 and 1 of the input switch control register (ISC) (see Figure 12-11) The peripheral functions used in the LIN communication operation are shown below. 226 User's Manual U15836EJ4V0UD CHAPTER 12 SERIAL INTERFACE UART6 12.2 Configuration of Serial Interface UART6 Serial interface UART6 includes the following hardware. Table 12-1. Configuration of Serial Interface UART6 Item Registers Receive buffer register 6 (RXB6) Receive shift register 6 (RXS6) Transmit buffer register 6 (TXB6) Transmit shift register 6 (TXS6) Control registers Asynchronous serial interface operation mode register 6 (ASIM6) Asynchronous serial interface reception error status register 6 (ASIS6) Asynchronous serial interface transmission status register 6 (ASIF6) Clock selection register 6 (CKSR6) Baud rate generator control register 6 (BRGC6) Asynchronous serial interface control register 6 (ASICL6) Input switch control register (ISC) Port mode register 1 (PM1) Port register 1 (P1) Configuration User's Manual U15836EJ4V0UD 227 Selector 228 fX fX/2 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 fX/28 fX/29 fX/210 8-bit timer/ event counter 50 output Asynchronous serial interface operation mode register 6 (ASIM6) Figure 12-4. Block Diagram of Serial Interface UART6 TI000, INTP0Note Filter INTSR6 INTSRE6 RXD6/ P14 Reception control Receive shift register 6 (RXS6) Asynchronous serial interface control register 6 (ASICL6) Receive buffer register 6 (RXB6) Asynchronous serial interface reception error status register 6 (ASIS6) Baud rate generator Reception unit Internal bus CHAPTER 12 SERIAL INTERFACE UART6 User's Manual U15836EJ4V0UD Baud rate generator control register 6 (BRGC6) 8 Asynchronous serial Clock selection interface transmission register 6 (CKSR6) status register 6 (ASIF6) 8 Baud rate generator Asynchronous serial interface control register 6 (ASICL6) Transmit buffer register 6 (TXB6) INTST6 Transmission control Transmit shift register 6 (TXS6) TXD6/ P13 Registers Output latch (P13) Transmission unit PM13 Note Selectable with input switch control register (ISC). CHAPTER 12 SERIAL INTERFACE UART6 (1) Receive buffer register 6 (RXB6) This 8-bit register stores parallel data converted by receive shift register 6 (RXS6). Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register 6 (RXS6). If the data length is set to 7 bits, data is transferred as follows. * In LSB-first reception, the receive data is transferred to bits 0 to 6 of RXB6 and the MSB of RXB6 is always 0. * In MSB-first reception, the receive data is transferred to bits 1 to 7 of RXB6 and the LSB of RXB6 is always 0. If an overrun error (OVE6) occurs, the receive data is not transferred to RXB6. RXB6 can be read by an 8-bit memory manipulation instruction. No data can be written to this register. RESET input sets this register to FFH. (2) Receive shift register 6 (RXS6) This register converts the serial data input to the RXD6 pin into parallel data. RXS6 cannot be directly manipulated by a program. (3) Transmit buffer register 6 (TXB6) This buffer register is used to set transmit data. Transmission is started when data is written to TXB6. This register can be read or written by an 8-bit memory manipulation instruction. RESET input sets this register to FFH. Cautions 1. Do not write data to TXB6 when bit 1 (TXBF6) of asynchronous serial interface transmission status register 6 (ASIF6) is 1. 2. Do not refresh (write the same value to) TXB6 by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of asynchronous serial interface operation mode register 6 (ASIM6) are 1 or when bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 are 1). (4) Transmit shift register 6 (TXS6) This register transmits the data transferred from TXB6 from the TXD6 pin as serial data. Data is transferred from TXB6 immediately after TXB6 is written for the first transmission, or immediately before INTST6 occurs after one frame was transmitted for continuous transmission. Data is transferred from TXB6 and transmitted from the TXD6 pin at the falling edge of the base clock. TXS6 cannot be directly manipulated by a program. User's Manual U15836EJ4V0UD 229 CHAPTER 12 SERIAL INTERFACE UART6 12.3 Registers Controlling Serial Interface UART6 Serial interface UART6 is controlled by the following nine registers. * Asynchronous serial interface operation mode register 6 (ASIM6) * Asynchronous serial interface reception error status register 6 (ASIS6) * Asynchronous serial interface transmission status register 6 (ASIF6) * Clock selection register 6 (CKSR6) * Baud rate generator control register 6 (BRGC6) * Asynchronous serial interface control register 6 (ASICL6) * Input switch control register (ISC) * Port mode register 1 (PM1) * Port register 1 (P1) (1) Asynchronous serial interface operation mode register 6 (ASIM6) This 8-bit register controls the serial communication operations of serial interface UART6. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 01H. Remark ASIM6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1). Figure 12-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (1/2) Address: FF50H After reset: 01H R/W Symbol ASIM6 <7> POWER6 <6> TXE6 <5> RXE6 4 PS61 3 PS60 2 CL6 1 SL6 0 ISRM6 POWER6 0 Note 1 Enables/disables operation of internal operation clock Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit Note 2 . 1 Note 3 Enables operation of the internal operation clock TXE6 0 1 Enables/disables transmission Disables transmission (synchronously resets the transmission circuit). Enables transmission Notes 1. 2. The output of the TXD6 pin goes high and the input from the RXD6 pin is fixed to the high level when POWER6 = 0. Asynchronous serial interface reception error status register 6 (ASIS6), asynchronous serial interface transmission status register 6 (ASIF6), bit 7 (SBRF6) and bit 6 (SBRT6) of asynchronous serial interface control register 6 (ASICL6), and receive buffer register 6 (RXB6) are reset. 3. Operation of the 8-bit counter output is enabled at the second base clock after 1 is written to the POWER6 bit. 230 User's Manual U15836EJ4V0UD CHAPTER 12 SERIAL INTERFACE UART6 Figure 12-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (2/2) RXE6 0 1 Enables/disables reception Disables reception (synchronously resets the reception circuit). Enables reception PS61 0 0 1 1 PS60 0 1 0 1 Transmission operation Does not output parity bit. Outputs 0 parity. Outputs odd parity. Outputs even parity. Reception operation Reception without parity Reception as 0 parity Note Judges as odd parity. Judges as even parity. CL6 0 1 Specifies character length of transmit/receive data Character length of data = 7 bits Character length of data = 8 bits SL6 0 1 Number of stop bits = 1 Number of stop bits = 2 Specifies number of stop bits of transmit data ISRM6 0 1 Enables/disables occurrence of reception completion interrupt in case of error "INTSRE6" occurs in case of error (at this time, INTSR6 does not occur). "INTSR6" occurs in case of error (at this time, INTSRE6 does not occur). Note If "reception as 0 parity" is selected, the parity is not judged. Therefore, bit 2 (PE6) of asynchronous serial interface reception error status register 6 (ASIS6) is not set and the error interrupt does not occur. Cautions 1. At startup, set POWER6 to 1 and then set TXE6 to 1. To stop the operation, clear TXE6 to 0 and then clear POWER6 to 0. 2. At startup, set POWER6 to 1 and then set RXE6 to 1. To stop the operation, clear RXE6 to 0 and then clear POWER6 to 0. 3. Set POWER6 to 1 and then set RXE6 to 1 while a high level is input to the RxD6 pin. If POWER6 is set to 1 and RXE6 is set to 1 while a low level is input, reception is started. 4. Clear the TXE6 and RXE6 bits to 0 before rewriting the PS61, PS60, and CL6 bits. 5. Fix the PS61 and PS60 bits to 0 when mounting the device on LIN. 6. Make sure that TXE6 = 0 when rewriting the SL6 bit. Reception is always performed with "the number of stop bits = 1", and therefore, is not affected by the set value of the SL6 bit. 7. Make sure that RXE6 = 0 when rewriting the ISRM6 bit. User's Manual U15836EJ4V0UD 231 CHAPTER 12 SERIAL INTERFACE UART6 (2) Asynchronous serial interface reception error status register 6 (ASIS6) This register indicates an error status on completion of reception by serial interface UART6. It includes three error flag bits (PE6, FE6, OVE6). This register is read-only by an 8-bit memory manipulation instruction. RESET input clears this register to 00H if bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 0. 00H is read when this register is read. Figure 12-6. Format of Asynchronous Serial Interface Reception Error Status Register 6 (ASIS6) Address: FF53H After reset: 00H R Symbol ASIS6 7 0 6 0 5 0 4 0 3 0 2 PE6 1 FE6 0 OVE6 PE6 0 1 Status flag indicating parity error If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read If the parity of transmit data does not match the parity bit on completion of reception FE6 0 1 Status flag indicating framing error If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read If the stop bit is not detected on completion of reception OVE6 0 1 Status flag indicating overrun error If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read If receive data is set to the RXB register and the next reception operation is completed before the data is read. Cautions 1. The operation of the PE6 bit differs depending on the set values of the PS61 and PS60 bits of asynchronous serial interface operation mode register 6 (ASIM6). 2. The first bit of the receive data is checked as the stop bit, regardless of the number of stop bits. 3. If an overrun error occurs, the next receive data is not written to receive buffer register 6 (RXB6) but discarded. 4. If data is read from ASIS6, a wait cycle is generated. CAUTIONS FOR WAIT. For details, see CHAPTER 28 232 User's Manual U15836EJ4V0UD CHAPTER 12 SERIAL INTERFACE UART6 (3) Asynchronous serial interface transmission status register 6 (ASIF6) This register indicates the status of transmission by serial interface UART6. It includes two status flag bits (TXBF6 and TXSF6). Transmission can be continued without disruption even during an interrupt period, by writing the next data to the TXB6 register after data has been transferred from the TXB6 register to the TXS6 register. This register is read-only by an 8-bit memory manipulation instruction. RESET input clears this register to 00H if bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 0. Figure 12-7. Format of Asynchronous Serial Interface Transmission Status Register 6 (ASIF6) Address: FF55H After reset: 00H R Symbol ASIF6 7 0 6 0 5 0 4 0 3 0 2 0 1 TXBF6 0 TXSF6 TXBF6 0 1 Transmit buffer data flag If POWER6 = 0 or TXE6 = 0, or if data is transferred to transmit shift register 6 (TXS6) If data is written to transmit buffer register 6 (TXB6) (if data exists in TXB6) TXSF6 0 Transmit shift register data flag If POWER6 = 0 or TXE6 = 0, or if the next data is not transferred from transmit buffer register 6 (TXB6) after completion of transfer 1 If data is transferred from transmit buffer register 6 (TXB6) (if data transmission is in progress) Cautions 1. To transmit data continuously, write the first transmit data (first byte) to the TXB6 register. Be sure to check that the TXBF6 flag is "0". If so, write the next transmit data (second byte) to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is "1", the transmit data cannot be guaranteed. 2. To initialize the transmission unit upon completion of continuous transmission, be sure to check that the TXSF6 flag is "0" after generation of the transmission completion interrupt, and then execute initialization. If initialization is executed while the TXSF6 flag is "1", the transmit data cannot be guaranteed. User's Manual U15836EJ4V0UD 233 CHAPTER 12 SERIAL INTERFACE UART6 (4) Clock selection register 6 (CKSR6) This register selects the base clock of serial interface UART6. CKSR6 can be set by an 8-bit memory manipulation instruction. RESET input clears this register to 00H. Remark CKSR6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1). Figure 12-8. Format of Clock Selection Register 6 (CKSR6) Address: FF56H After reset: 00H R/W Symbol CKSR6 7 0 6 0 5 0 4 0 3 TPS63 2 TPS62 1 TPS61 0 TPS60 TPS63 0 0 0 0 0 0 0 0 1 1 1 1 TPS62 0 0 0 0 1 1 1 1 0 0 0 0 Other TPS61 0 0 1 1 0 0 1 1 0 0 1 1 TPS60 0 1 0 1 0 1 0 1 0 1 0 1 fX (10 MHz) fX/2 (5 MHz) Base clock (fXCLK6) selection fX/2 (2.5 MHz) fX/2 (1.25 MHz) fX/2 (625 kHz) fX/2 (312.5 kHz) fX/2 (156.25 kHz) fX/2 (78.13 kHz) fX/2 (39.06 kHz) fX/2 (19.53 kHz) fX/2 (9.77 kHz) TM50 output Note 10 9 8 7 6 5 4 3 2 Setting prohibited Note To select the output of TM50 as the base clock, start the operation by setting 8-bit timer/event counter 50 so that the duty is 50% of the output in the PWM mode (bit 6 (TMC506) of the TMC50 register = 1), and then set TPS63, TPS62, TPS61, and TPS60 to 1, 0, 1, and 1, respectively. It is not necessary to enable the TO50 pin as a timer output pin (bit 0 (TOE50) of the TMC register may be 0 or 1). Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the Ring-OSC oscillator is divided and supplied as the count clock. If the base clock is the RingOSC clock, the operation of serial interface UART6 is not guaranteed. 2. Make sure POWER6 = 0 when rewriting TPS63 to TPS60. Remarks 1. Figures in parentheses are for operation with fX = 10 MHz 2. fX: X1 input clock oscillation frequency 234 User's Manual U15836EJ4V0UD CHAPTER 12 SERIAL INTERFACE UART6 (5) Baud rate generator control register 6 (BRGC6) This register sets the division value of the 8-bit counter of serial interface UART6. BRGC6 can be set by an 8-bit memory manipulation instruction. RESET input sets this register to FFH. Remark BRGC6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1). Figure 12-9. Format of Baud Rate Generator Control Register 6 (BRGC6) Address: FF57H After reset: FFH R/W Symbol BRGC6 7 MDL67 6 MDL66 5 MDL65 4 MDL64 3 MDL63 2 MDL62 1 MDL61 0 MDL60 MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 x 0 0 0 * * * * * 1 1 1 1 MDL61 x 0 0 1 * * * * * 0 0 1 1 MDL60 x 0 1 0 * * * * * 0 1 0 1 k x 8 9 10 * * * * * 252 253 254 255 Output clock selection of 8-bit counter 0 0 0 0 * * * * * 1 1 1 1 0 0 0 0 * * * * * 1 1 1 1 0 0 0 0 * * * * * 1 1 1 1 0 0 0 0 * * * * * 1 1 1 1 0 1 1 1 * * * * * 1 1 1 1 Setting prohibited fXCLK6/8 fXCLK6/9 fXCLK6/10 * * * * * fXCLK6/252 fXCLK6/253 fXCLK6/254 fXCLK6/255 Cautions 1. Make sure that bit 6 (TXE6) and bit 5 (RXE6) of the ASIM6 register = 0 when rewriting the MDL67 to MDL60 bits. 2. The baud rate value is the output clock of the 8-bit counter divided by 2. Remarks 1. fXCLK6: Frequency of base clock selected by the TPS63 to TPS60 bits of CKSR6 register 2. k: 3. x: Value set by MDL67 to MDL60 bits (k = 8, 9, 10, ..., 255) Don't care User's Manual U15836EJ4V0UD 235 CHAPTER 12 SERIAL INTERFACE UART6 (6) Asynchronous serial interface control register 6 (ASICL6) This register controls the serial communication operations of serial interface UART6. ASICL6 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 16H. Caution ASICL6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1). Note, however, that communication is started by the refresh operation because bit 6 (SBRT6) of ASICL6 is cleared to 0 when communication is completed (when an interrupt signal is generated). Figure 12-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) Address: FF58H After reset: 16H R/W Symbol ASICL6 <7> SBRF6 <6> SBRT6 Note 5 0 4 1 3 0 2 1 1 DIR6 0 TXDLV6 SBRF6 0 1 SBF reception status flag If POWER6 = 0 and RXE6 = 0 or if SBF reception has been completed correctly SBF reception in progress SBRT6 0 1 SBF reception trigger SBF reception trigger - DIR6 0 1 MSB LSB First bit specification TXDLV6 0 1 Normal output of TXD6 Inverted output of TXD6 Enables/disables inverting TXD6 output Note Bits 2 to 5 and 7 are read-only. Cautions 1. In the case of an SBF reception error, return the mode to the SBF reception mode and hold the status of the SBRF6 flag. 2. Before setting the SBRT6 bit, make sure that bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1. 3. The read value of the SBRT6 bit is always 0. SBRT6 is automatically cleared to 0 after SBF reception has been correctly completed. 4. Before rewriting the DIR6 and TXDLV6 bits, clear the TXE6 and RXE6 bits to 0. 236 User's Manual U15836EJ4V0UD CHAPTER 12 SERIAL INTERFACE UART6 (7) Input switch control register (ISC) The input switch control register (ISC) is used to receive a status signal transmitted from the master during LIN (Local Interconnect Network) reception. The input signal is switched by setting ISC. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 12-11. Format of Input Switch Control Register (ISC) Address: FF4FH Symbol ISC After reset: 00H 7 0 6 0 R/W 5 0 4 0 3 0 2 0 1 ISC1 0 ISC0 ISC1 0 1 TI000 (P00) RxD6 (P14) TI000 input source selection ISC0 0 1 INTP0 (P120) RxD6 (P14) INTP0 input source selection (8) Port mode register 1 (PM1) This register sets port 1 input/output in 1-bit units. When using the P13/TxD6 pin for serial interface data output, clear PM13 to 0 and set the output latch of P13 to 1. Set PM14 to 1 when using the P14/RxD6 pin as a serial interface data input pin. The output latch of P14 at this time may be 0 or 1. PM1 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to FFH. Figure 12-12. Format of Port Mode Register 1 (PM1) Address: FF21H Symbol PM1 7 PM17 After reset: FFH 6 PM16 R/W 5 PM15 4 PM14 3 PM13 2 PM12 1 PM11 0 PM10 PM1n 0 1 P1n pin I/O mode selection (n = 0 to 7) Output mode (output buffer on) Input mode (output buffer off) User's Manual U15836EJ4V0UD 237 CHAPTER 12 SERIAL INTERFACE UART6 12.4 Operation of Serial Interface UART6 Serial interface UART6 has the following two modes. * Operation stop mode * Asynchronous serial interface (UART) mode 12.4.1 Operation stop mode In this mode, serial communication cannot be executed; therefore, the power consumption can be reduced. In addition, the pins can be used as ordinary port pins in this mode. To set the operation stop mode, clear bits 7, 6, and 5 (POWER6, TXE6, and RXE6) of ASIM6 to 0. (1) Register used The operation stop mode is set by asynchronous serial interface operation mode register 6 (ASIM6). ASIM6 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 01H. Address: FF50H After reset: 01H R/W Symbol ASIM6 <7> POWER6 <6> TXE6 <5> RXE6 4 PS61 3 PS60 2 CL6 1 SL6 0 ISRM6 POWER6 0 Note 1 Enables/disables operation of internal operation clock Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit Note 2 . TXE6 0 Enables/disables transmission Disables transmission operation (synchronously resets the transmission circuit). RXE6 0 Enables/disables reception Disables reception (synchronously resets the reception circuit). Notes 1. 2. The output of the TXD6 pin goes high and the input from the RXD6 pin is fixed to high level when POWER6 = 0. Asynchronous serial interface reception error status register 6 (ASIS6), asynchronous serial interface transmission status register 6 (ASIF6), bit 7 (SBRF6) and bit 6 (SBRT6) of asynchronous serial interface control register 6 (ASICL6), and receive buffer register 6 (RXB6) are reset. Caution Clear POWER6 to 0 after clearing TXE6 and RXE6 to 0 to set the operation stop mode. To start the operation, set POWER6 to 1, and then set TXE6 and RXE6 to 1. Remark To use the RxD6/P14 and TxD6/P13 pins as general-purpose port pins, see CHAPTER 4 FUNCTIONS. PORT 238 User's Manual U15836EJ4V0UD CHAPTER 12 SERIAL INTERFACE UART6 12.4.2 Asynchronous serial interface (UART) mode In this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates. (1) Registers used * Asynchronous serial interface operation mode register 6 (ASIM6) * Asynchronous serial interface reception error status register 6 (ASIS6) * Asynchronous serial interface transmission status register 6 (ASIF6) * Clock selection register 6 (CKSR6) * Baud rate generator control register 6 (BRGC6) * Asynchronous serial interface control register 6 (ASICL6) * Input switch control register (ISC) * Port mode register 1 (PM1) * Port register 1 (P1) The basic procedure of setting an operation in the UART mode is as follows. <1> Set the CKSR6 register (see Figure 12-8). <2> Set the BRGC6 register (see Figure 12-9). <3> Set bits 0 to 4 (ISRM6, SL6, CL6, PS60, PS61) of the ASIM6 register (see Figure 12-5). <4> Set bits 0 and 1 (TXDLV6, DIR6) of the ASICL6 register (see Figure 12-10). <5> Set bit 7 (POWER6) of the ASIM6 register to 1. <6> Set bit 6 (TXE6) of the ASIM6 register to 1. Transmission is enabled. Set bit 5 (RXE6) of the ASIM6 register to 1. Reception is enabled. <7> Write data to transmit buffer register 6 (TXB6). Data transmission is started. Caution Take relationship with the other party of communication when setting the port mode register and port register. User's Manual U15836EJ4V0UD 239 CHAPTER 12 SERIAL INTERFACE UART6 The relationship between the register settings and pins is shown below. Table 12-2. Relationship Between Register Settings and Pins POWER6 TXE6 RXE6 PM13 P13 PM14 P14 UART6 Operation 0 1 0 0 1 1 0 1 0 1 x x Note Pin Function TxD6/P13 P13 P13 TxD6 TxD6 RxD6/P14 P14 RxD6 P14 RxD6 x x Note x Note x Note Stop Reception Transmission Transmission/ reception Note Note 1 x Note x x Note 0 0 1 1 1 x Note Can be set as port function. Remark x: TXE6: RXE6: PM1x: P1x: don't care Bit 6 of ASIM6 Bit 5 of ASIM6 Port mode register Port output latch POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6) 240 User's Manual U15836EJ4V0UD CHAPTER 12 SERIAL INTERFACE UART6 (2) Communication operation (a) Format and waveform example of normal transmit/receive data Figures 12-13 and 12-14 show the format and waveform example of the normal transmit/receive data. Figure 12-13. Format of Normal UART Transmit/Receive Data 1. LSB-first transmission/reception 1 data frame Start bit D0 D1 D2 D3 D4 D5 D6 D7 Parity bit Stop bit Character bits 2. MSB-first transmission/reception 1 data frame Start bit D7 D6 D5 D4 D3 D2 D1 D0 Parity bit Stop bit Character bits One data frame consists of the following bits. * Start bit ... 1 bit * Character bits ... 7 or 8 bits * Parity bit ... Even parity, odd parity, 0 parity, or no parity * Stop bit ... 1 or 2 bits The character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial interface operation mode register 6 (ASIM6). Whether data is communicated with the LSB or MSB first is specified by bit 1 (DIR6) of asynchronous serial interface control register 6 (ASICL6). Whether the TXD6 pin outputs normal or inverted data is specified by bit 0 (TXDLV6) of ASICL6. User's Manual U15836EJ4V0UD 241 CHAPTER 12 SERIAL INTERFACE UART6 Figure 12-14. Example of Normal UART Transmit/Receive Data Waveform 1. Data length: 8 bits, LSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop 2. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop 3. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H, TXD6 pin inverted output 1 data frame Start D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop 4. Data length: 7 bits, LSB first, Parity: Odd parity, Stop bit: 2 bits, Communication data: 36H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 Parity Stop Stop 5. Data length: 8 bits, LSB first, Parity: None, Stop bit: 1 bit, Communication data: 87H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 D7 Stop 242 User's Manual U15836EJ4V0UD CHAPTER 12 SERIAL INTERFACE UART6 (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected. With zero parity and no parity, an error cannot be detected. Caution Fix the PS61 and PS60 bits to 0 when the device is incorporated in LIN. (i) Even parity * Transmission Transmit data, including the parity bit, is controlled so that the number of bits that are "1" is even. The value of the parity bit is as follows. If transmit data has an odd number of bits that are "1": 1 If transmit data has an even number of bits that are "1": 0 * Reception The number of bits that are "1" in the receive data, including the parity bit, is counted. If it is odd, a parity error occurs. (ii) Odd parity * Transmission Unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that are "1" is odd. If transmit data has an odd number of bits that are "1": 0 If transmit data has an even number of bits that are "1": 1 * Reception The number of bits that are "1" in the receive data, including the parity bit, is counted. If it is even, a parity error occurs. (iii) 0 parity The parity bit is cleared to 0 when data is transmitted, regardless of the transmit data. The parity bit is not detected when the data is received. Therefore, a parity error does not occur regardless of whether the parity bit is "0" or "1". (iv) No parity No parity bit is appended to the transmit data. Reception is performed assuming that there is no parity bit when data is received. Because there is no parity bit, a parity error does not occur. User's Manual U15836EJ4V0UD 243 CHAPTER 12 SERIAL INTERFACE UART6 (c) Normal transmission The TXD6 pin outputs a high level when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1. If bit 6 (TXE6) of ASIM6 is then set to 1, transmission is enabled. Transmission can be started by writing transmit data to transmit buffer register 6 (TXB6). The start bit, parity bit, and stop bit are automatically appended to the data. When transmission is started, the data in TXB6 is transferred to transmit shift register 6 (TXS6). After that, the data is sequentially output from TXS6 to the TXD6 pin. When transmission is completed, the parity bit and stop bit set by ASIM6 are added and a transmission completion interrupt request (INTST6) is generated. Transmission is stopped until the data to be transmitted next is written to TXB6. Figure 12-15 shows the timing of the transmission completion interrupt request (INTST6). This interrupt occurs as soon as the last stop bit has been output. Figure 12-15. Normal Transmission Completion Interrupt Request Timing 1. Stop bit length: 1 TXD6 (output) Start D0 D1 D2 D6 D7 Parity Stop INTST6 2. Stop bit length: 2 TXD6 (output) Start D0 D1 D2 D6 D7 Parity Stop INTST6 244 User's Manual U15836EJ4V0UD CHAPTER 12 SERIAL INTERFACE UART6 (d) Continuous transmission The next transmit data can be written to transmit buffer register 6 (TXB6) as soon as transmit shift register 6 (TXS6) has started its shift operation. Consequently, even while the INTST6 interrupt is being serviced after transmission of one data frame, data can be continuously transmitted and an efficient communication rate can be realized. In addition, the TXB6 register can be efficiently written twice (2 bytes) without having to wait for the transmission time of one data frame, by reading bit 0 (TXSF6) of asynchronous serial interface transmission status register 6 (ASIF6) when the transmission completion interrupt has occurred. To transmit data continuously, be sure to reference the ASIF6 register to check the transmission status and whether the TXB6 register can be written, and then write the data. Cautions 1. The TXBF6 and TXSF6 flags of the ASIS register change from "10" to "11", and to "01" during continuous transmission. To check the status, therefore, do not use a combination of the TXBF6 and TXSF6 flags for judgment. Read only the TXBF6 flag when executing continuous transmission. 2. When the device is incorporated in a LIN, the continuous transmission function cannot be used. Make sure that asynchronous serial interface transmission status register 6 (ASIF6) is 00H before writing transmit data to transmit buffer register 6 (TXB6). TXBF6 0 1 Writing enabled Writing disabled Writing to TXB6 Register Caution To transmit data continuously, write the first transmit data (first byte) to the TXB6 register. Be sure to check that the TXBF6 flag is "0". If so, write the next transmit data (second byte) to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is "1", the transmit data cannot be guaranteed. The communication status can be checked using the TXSF6 flag. TXSF6 0 1 Transmission is completed. Transmission is in progress. Transmission Status Cautions 1. To initialize the transmission unit upon completion of continuous transmission, be sure to check that the TXSF6 flag is "0" after generation of the transmission completion interrupt, and then execute initialization. If initialization is executed while the TXSF6 flag is "1", the transmit data cannot be guaranteed. 2. During continuous transmission, an overrun error may occur, which means that the next transmission was completed before execution of INTST6 interrupt servicing after transmission of one data frame. An overrun error can be detected by developing a program that can count the number of transmit data and by referencing the TXSF6 flag. User's Manual U15836EJ4V0UD 245 CHAPTER 12 SERIAL INTERFACE UART6 Figure 12-16 shows an example of the continuous transmission processing flow. Figure 12-16. Example of Continuous Transmission Processing Flow Set registers. Write TXB6. Transfer executed necessary number of times? No Yes Read ASIF6 TXBF6 = 0? Yes No Write TXB6. Transmission completion interrupt occurs? Yes No Transfer executed necessary number of times? No Yes Read ASIF6 TXSF6 = 0? Yes Yes Completion of transmission processing No Remark TXB6: Transmit buffer register 6 ASIF6: Asynchronous serial interface transmission status register 6 TXBF6: Bit 1 of ASIF6 (transmit buffer data flag) TXSF6: Bit 0 of ASIF6 (transmit shift register data flag) 246 User's Manual U15836EJ4V0UD CHAPTER 12 SERIAL INTERFACE UART6 Figure 12-17 shows the timing of starting continuous transmission, and Figure 12-18 shows the timing of ending continuous transmission. Figure 12-17. Timing of Starting Continuous Transmission TXD6 INTST6 Start Data (1) Parity Stop Start Data (2) Parity Stop Start TXB6 FF Data (1) Data (2) Data (3) TXS6 TXBF6 TXSF6 FF Data (1) Data (2) Data (3) Note Note When ASIF6 is read, there is a period in which TXBF6 and TXSF6 = 1, 1. Therefore, judge whether writing is enabled using only the TXBF6 bit. Remark TXD6: TXB6: TXS6: ASIF6: TXD6 pin (output) Transmit buffer register 6 Transmit shift register 6 Asynchronous serial interface transmission status register 6 INTST6: Interrupt request signal TXBF6: Bit 1 of ASIF6 TXSF6: Bit 0 of ASIF6 User's Manual U15836EJ4V0UD 247 CHAPTER 12 SERIAL INTERFACE UART6 Figure 12-18. Timing of Ending Continuous Transmission TXD6 INTST6 Stop Start Data (n - 1) Parity Stop Start Data (n) Parity Stop TXB6 Data (n - 1) Data (n) TXS6 Data (n - 1) Data (n) FF TXBF6 TXSF6 POWER6 or TXE6 Remark TXD6: INTST6: TXB6: TXS6: ASIF6: TXBF6: TXSF6: TXE6: TXD6 pin (output) Interrupt request signal Transmit buffer register 6 Transmit shift register 6 Asynchronous serial interface transmission status register 6 Bit 1 of ASIF6 Bit 0 of ASIF6 Bit 6 of asynchronous serial interface operation mode register (ASIM6) POWER6: Bit 7 of asynchronous serial interface operation mode register (ASIM6) 248 User's Manual U15836EJ4V0UD CHAPTER 12 SERIAL INTERFACE UART6 (e) Normal reception Reception is enabled and the RXD6 pin input is sampled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. The 8-bit counter of the baud rate generator starts counting when the falling edge of the RXD6 pin input is detected. When the set value of baud rate generator control register 6 (BRGC6) has been counted, the RXD6 pin input is sampled again ( as a start bit. When the start bit is detected, reception is started, and serial data is sequentially stored in the receive shift register (RXS6) at the set baud rate. When the stop bit has been received, the reception completion interrupt (INTSR6) is generated and the data of RXS6 is written to receive buffer register 6 (RXB6). If an overrun error (OVE6) occurs, however, the receive data is not written to RXB6. Even if a parity error (PE6) occurs while reception is in progress, reception continues to the reception position of the stop bit, and an error interrupt (INTSR6/INTSRE6) is generated on completion of reception. Figure 12-19. Reception Completion Interrupt Request Timing in Figure 12-19). If the RXD6 pin is low level at this time, it is recognized RXD6 (input) Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop INTSR6 RXB6 Cautions 1. Be sure to read receive buffer register 6 (RXB6) even if a reception error occurs. Otherwise, an overrun error will occur when the next data is received, and the reception error status will persist. 2. Reception is always performed with the "number of stop bits = 1". The second stop bit is ignored. 3. Be sure to read asynchronous serial interface reception error status register 6 (ASIS6) before reading RXB6. User's Manual U15836EJ4V0UD 249 CHAPTER 12 SERIAL INTERFACE UART6 (f) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 6 (ASIS6) is set as a result of data reception, a reception error interrupt request (INTSR6/INTSRE6) is generated. Which error has occurred during reception can be identified by reading the contents of ASIS6 in the reception error interrupt servicing (INTSR6/INTSRE6) (see Figure 12-6). The contents of ASIS6 are reset to 0 when ASIS6 is read. Table 12-3. Cause of Reception Error Reception Error Parity error Cause The parity specified for transmission does not match the parity of the receive data. Framing error Overrun error Stop bit is not detected. Reception of the next data is completed before data is read from receive buffer register 6 (RXB6). The error interrupt can be separated into reception completion interrupt (INTSR6) and error interrupt (INTSRE6) by clearing bit 0 (ISRM6) of asynchronous serial interface operation mode register 6 (ASIM6) to 0. Figure 12-20. Reception Error Interrupt 1. If ISRM6 is cleared to 0 (reception completion interrupt (INTSR6) and error interrupt (INTSRE6) are separated) (a) No error during reception INTSR6 (b) Error during reception INTSR6 INTSRE6 INTSRE6 2. If ISRM6 is set to 1 (error interrupt is included in INTSR6) (a) No error during reception (b) Error during reception INTSR6 INTSRE6 INTSR6 INTSRE6 250 User's Manual U15836EJ4V0UD CHAPTER 12 SERIAL INTERFACE UART6 (g) Noise filter of receive data The RXD6 signal is sampled with the base clock output by the prescaler block. If two sampled values are the same, the output of the match detector changes, and the data is sampled as input data. Because the circuit is configured as shown in Figure 12-21, the internal processing of the reception operation is delayed by two clocks from the external signal status. Figure 12-21. Noise Filter Circuit Base clock RXD6/P14 In Q Internal signal A In Q Internal signal B Match detector LD_EN (h) SBF transmission When the device is incorporated in LIN, the SBF (Synchronous Break Field) transmission control function is used for transmission. Operation. SBF transmission is used to transmit an SBF length that is a low-level width of 13 bits or more by adjusting the baud rate value of the ordinary UART transmission function. [Setting method] Transmit 00H by setting the number of character bits of the data to 8 bits and the parity bit to 0 parity or even parity. This enables a low-level transmission of a data frame consisting of 10 bits (1 bit (start bit) + 8 bits (character bits) + 1 bit (parity bit)). Adjust the baud rate value to adjust this 10-bit low level to the targeted SBF length. Example If LIN is to be transmitted under the following conditions * Base clock of UART6 = 5 MHz (set by clock selection register 6 (CKSR6)) * Target baud rate value = 19200 bps To realize the above baud rate value, the length of a 13-bit SBF is as follows if the baud rate generator control register 6 (BRGC6) is set to 130. * 13-bit SBF length = 0.2 s x 130 x 2 x 13 = 676 s To realize a 13-bit SBF length in 10 bits, set a value 1.3 times the targeted baud rate to BRGC6. In this example, set 169 to BRGC6. The transmission length of a 10-bit low level in this case is as follows, and matches the 13-bit SBF length. * 10-bit low-level transmission length = 0.2 s x 169 x 2 x 10 = 676 s For the transmission operation of LIN, see Figure 12-1 LIN Transmission User's Manual U15836EJ4V0UD 251 CHAPTER 12 SERIAL INTERFACE UART6 If the number of bits set by BRGC6 runs short, adjust the number of bits by setting the base clock of UART6. Figure 12-22. Example of Setting Procedure of SBF Transmission (Flowchart) Start Read BRGC6 register and save current set value of BRGC6 register to generalpurpose register. Clear TXE6 and RXE6 bits of ASIM6 register to 0 (to disable transmission/ reception). Set value to BRGC6 register to realize desired SBF length. Clear TXE6 and RXE6 bits of ASIM6 register to 0. Set character length of data to 8 bits and parity to 0 or even using ASIM6 register. Rewrite saved BRGC6 value to BRGC6 register. Set TXE6 bit of ASIM6 register to 1 to enable transmission. Re-set PS61 bit, PS60 bit, and CL6 bit of ASIM6 register to desired value. Set TXB6 register to "00H" and start transmission. Set TXE6 bit of ASIM6 register to 1 to enable transmission. End No INTST6 occurred? Yes Figure 12-23. SBF Transmission TXD6 1 2 3 4 5 6 7 8 9 10 11 12 13 Stop INTST6 Remark TXD6: TXD6 pin (output) INTST6: Transmission completion interrupt request 252 User's Manual U15836EJ4V0UD CHAPTER 12 SERIAL INTERFACE UART6 (i) SBF reception When the device is incorporated in LIN, the SBF (Synchronous Break Field) reception control function is used for reception. For the reception operation of LIN, see Figure 12-2 LIN Reception Operation. Reception is enabled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. SBF reception is enabled when bit 6 (SBRT6) of asynchronous serial interface control register 6 (ASICL6) is set to 1. In the SBF reception enabled status, the RXD6 pin is sampled and the start bit is detected in the same manner as the normal reception enable status. When the start bit has been detected, reception is started, and serial data is sequentially stored in receive shift register 6 (RXS6) at the set baud rate. When the stop bit is received and if the width of SBF is 11 bits or more, a reception completion interrupt request (INTSR6) is generated as normal processing. At this time, the SBRF6 and SBRT6 bits are automatically cleared, and SBF reception ends. Detection of errors, such as OVE6, PE6, and FE6 (bits 0 to 2 of asynchronous serial interface reception error status register 6 (ASIS6)) is suppressed, and error detection processing of UART communication is not performed. In addition, data transfer between receive shift register 6 (RXS6) and receive buffer register 6 (RXB6) is not performed, and the reset value of FFH is retained. If the width of SBF is 10 bits or less, an interrupt does not occur as error processing after the stop bit has been received, and the SBF reception mode is restored. In this case, the SBRF6 and SBRT6 bits are not cleared. Figure 12-24. SBF Reception 1. Normal SBF reception (stop bit is detected with a width of more than 10.5 bits) RXD6 1 2 3 4 5 6 7 8 9 10 11 SBRT6 /SBRF6 INTSR6 2. SBF reception error (stop bit is detected with a width of 10.5 bits or less) RXD6 1 2 3 4 5 6 7 8 9 10 SBRT6 /SBRF6 INTSR6 "0" Remark RXD6: RXD6 pin (input) SBRT6: Bit 6 of asynchronous serial interface control register 6 (ASICL6) SBRF6: Bit 7 of ASICL6 INTSR6: Reception completion interrupt request User's Manual U15836EJ4V0UD 253 CHAPTER 12 SERIAL INTERFACE UART6 12.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and generates a serial clock for transmission/reception of UART6. Separate 8-bit counters are provided for transmission and reception. (1) Configuration of baud rate generator * Base clock The clock selected by bits 3 to 0 (TPS63 to TPS60) of clock selection register 6 (CKSR6) is supplied to each module when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is 1. This clock is called the base clock and its frequency is called fXCLK6. The base clock is fixed to low level when POWER6 = 0. * Transmission counter This counter stops, cleared to 0, when bit 7 (POWER6) or bit 6 (TXE6) of asynchronous serial interface operation mode register 6 (ASIM6) is 0. It starts counting when POWER6 = 1 and TXE6 = 1. The counter is cleared to 0 when the first data transmitted is written to transmit buffer register 6 (TXB6). If data are continuously transmitted, the counter is cleared to 0 again when one frame of data has been completely transmitted. If there is no data to be transmitted next, the counter is not cleared to 0 and continues counting until POWER6 or TXE6 is cleared to 0. * Reception counter This counter stops operation, cleared to 0, when bit 7 (POWER6) or bit 5 (RXE6) of asynchronous serial interface operation mode register 6 (ASIM6) is 0. It starts counting when the start bit has been detected. The counter stops operation after one frame has been received, until the next start bit is detected. 254 User's Manual U15836EJ4V0UD CHAPTER 12 SERIAL INTERFACE UART6 Figure 12-25. Configuration of Baud Rate Generator POWER6 fX fX/2 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 fX/28 fX/29 fX/210 8-bit timer/ event counter 50 output Baud rate generator POWER6, TXE6 (or RXE6) Selector fXCLK6 8-bit counter Match detector 1/2 Baud rate CKSR6: TPS63 to TPS60 BRGC6: MDL67 to MDL60 Remark POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6) TXE6: RXE6: CKSR6: BRGC6: Bit 6 of ASIM6 Bit 5 of ASIM6 Clock selection register 6 Baud rate generator control register 6 User's Manual U15836EJ4V0UD 255 CHAPTER 12 SERIAL INTERFACE UART6 (2) Generation of serial clock A serial clock can be generated by using clock selection register 6 (CKSR6) and baud rate generator control register 6 (BRGC6). Select the clock to be input to the 8-bit counter by using bits 3 to 0 (TPS63 to TPS60) of CKSR6. Bits 7 to 0 (MDL67 to MDL60) of BRGC6 can be used to select the division value of the 8-bit counter. (a) Baud rate The baud rate can be calculated by the following expression. * Baud rate = fXCLK6 2xk [bps] fXCLK6: Frequency of base clock selected by TPS63 to TPS60 bits of CKSR6 register k: Value set by MDL67 to MDL60 bits of BRGC6 register (k = 8, 9, 10, ..., 255) (b) Error of baud rate The baud rate error can be calculated by the following expression. * Error (%) = Actual baud rate (baud rate with error) Desired baud rate (correct baud rate) - 1 x 100 [%] Cautions 1. Keep the baud rate error during transmission to within the permissible error range at the reception destination. 2. Make sure that the baud rate error during reception satisfies the range shown in (4) Permissible baud rate range during reception. Example: Frequency of base clock = 10 MHz = 10,000,000 Hz Set value of MDL67 to MDL60 bits of BRGC6 register = 00100001B (k = 33) Target baud rate = 153600 bps Baud rate = 10 M/(2 x 33) = 10000000/(2 x 33) = 151515 [bps] Error = (151515/153600 - 1) x 100 = -1.357 [%] 256 User's Manual U15836EJ4V0UD CHAPTER 12 SERIAL INTERFACE UART6 (3) Example of setting baud rate Table 12-4. Set Data of Baud Rate Generator Baud Rate [bps] TPS63 to TPS60 600 1200 2400 4800 9600 10400 19200 31250 38400 76800 115200 153600 230400 6H 5H 4H 3H 2H 2H 1H 1H 0H 0H 0H 0H 0H 130 130 130 130 130 120 130 80 130 65 43 33 22 fX = 10.0 MHz k Calculated ERR[%] TPS63 to Value TPS60 601 1202 2404 4808 9615 10417 19231 31250 38462 76923 116279 151515 227272 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 0.16 0.94 -1.36 -1.36 6H 5H 4H 3H 2H 2H 1H 0H 0H 0H 0H 0H 0H fX = 8.38 MHz k Calculated ERR[%] TPS63 to Value TPS60 601 1201 2403 4805 9610 10371 19200 31268 38440 76182 116388 155185 232777 0.11 0.11 0.11 0.11 0.11 0.28 0.11 0.06 0.11 -0.80 1.03 1.03 1.03 5H 4H 3H 2H 1H 1H 0H 0H 0H 0H 0H 0H 0H fX = 4.19 MHz k Calculated ERR[%] Value 601 1201 2403 4805 9610 10475 19220 31268 38090 77593 116389 149643 232778 0.11 0.11 0.11 0.11 0.11 -0.28 0.11 0.06 -0.80 1.03 1.03 -2.58 1.03 109 109 109 109 109 101 109 134 109 55 36 27 18 109 109 109 109 109 101 109 67 55 27 18 14 9 Remark TPS63 to TPS60: Bits 3 to 0 of clock selection register 6 (CKSR6) (setting of base clock (fXCLK6)) k: fX: ERR: Value set by MDL67 to MDL60 bits of baud rate generator control register 6 (BRGC6) (k = 8, 9, 10, ..., 255) X1 input clock oscillation frequency Baud rate error User's Manual U15836EJ4V0UD 257 CHAPTER 12 SERIAL INTERFACE UART6 (4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below. Figure 12-26. Permissible Baud Rate Range During Reception Latch timing Data frame length of UART6 Start bit Bit 0 FL Bit 1 Bit 7 Parity bit Stop bit 1 data frame (11 x FL) Minimum permissible data frame length Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmin Maximum permissible data frame length Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmax As shown in Figure 12-26, the latch timing of the receive data is determined by the counter set by baud rate generator control register 6 (BRGC6) after the start bit has been detected. If the last data (stop bit) meets this latch timing, the data can be correctly received. Assuming that 11-bit data is received, the theoretical values can be calculated as follows. FL = (Brate)-1 Brate: Baud rate of UART6 k: FL: Set value of BRGC6 1-bit data length Margin of latch timing: 2 clocks Minimum permissible data frame length: FLmin = 11 x FL - k-2 2k x FL = 21k + 2 2k FL 258 User's Manual U15836EJ4V0UD CHAPTER 12 SERIAL INTERFACE UART6 Therefore, the maximum receivable baud rate at the transmission destination is as follows. BRmax = (FLmin/11)-1 = 22k 21k + 2 Brate Similarly, the maximum permissible data frame length can be calculated as follows. 10 11 x FLmax = 11 x FL - 21k - 2 20k k+2 2xk x FL = 21k - 2 2xk FL FLmax = FL x 11 Therefore, the minimum receivable baud rate at the transmission destination is as follows. BRmin = (FLmax/11)-1 = 20k 21k - 2 Brate The permissible baud rate error between UART6 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions, as follows. Table 12-5. Maximum/Minimum Permissible Baud Rate Error Division Ratio (k) 8 20 50 100 255 Maximum Permissible Baud Rate Error +3.53% +4.26% +4.56% +4.66% +4.72% Minimum Permissible Baud Rate Error -3.61% -4.31% -4.58% -4.67% -4.73% Remarks 1. The permissible error of reception depends on the number of bits in one frame, input clock frequency, and division ratio (k). The higher the input clock frequency and the higher the division ratio (k), the higher the permissible error. 2. k: Set value of BRGC6 User's Manual U15836EJ4V0UD 259 CHAPTER 12 SERIAL INTERFACE UART6 (5) Data frame length during continuous transmission When data is continuously transmitted, the data frame length from a stop bit to the next start bit is extended by two clocks of base clock from the normal value. However, the result of communication is not affected because the timing is initialized on the reception side when the start bit is detected. Figure 12-27. Data Frame Length During Continuous Transmission 1 data frame Start bit of second byte Bit 7 FL Parity bit FL Stop bit FLstp Start bit FL Bit 0 FL Start bit FL Bit 0 FL Bit 1 FL Where the 1-bit data length is FL, the stop bit length is FLstp, and base clock frequency is fXCLK6, the following expression is satisfied. FLstp = FL + 2/fXCLK6 Therefore, the data frame length during continuous transmission is: Data frame length = 11 x FL + 2/fXCLK6 260 User's Manual U15836EJ4V0UD CHAPTER 13 SERIAL INTERFACE CSI10 13.1 Functions of Serial Interface CSI10 Serial interface CSI10 has the following two modes. * Operation stop mode * 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial communication is not performed and can enable a reduction in the power consumption. For details, see 13.4.1 Operation stop mode. (2) 3-wire serial I/O mode (MSB/LSB-first selectable) This mode is used to communicate 8-bit data using three lines: a serial clock line (SCK10) and two serial data lines (SI10 and SO10). The processing time of data communication can be shortened in the 3-wire serial I/O mode because transmission and reception can be simultaneously executed. In addition, whether 8-bit data is communicated with the MSB or LSB first can be specified, so this interface can be connected to any device. The 3-wire serial I/O mode can be used connecting peripheral ICs and display controllers with a clocked serial interface. For details, see 13.4.2 3-wire serial I/O mode. 13.2 Configuration of Serial Interface CSI10 Serial interface CSI10 includes the following hardware. Table 13-1. Configuration of Serial Interface CSI10 Item Registers Configuration Transmit buffer register 10 (SOTB10) Serial I/O shift register 10 (SIO10) Transmit controller Clock start/stop controller & clock phase controller Control registers Serial operation mode register 10 (CSIM10) Serial clock selection register 10 (CSIC10) Port mode register 1 (PM1) Port register 1 (P1) User's Manual U15836EJ4V0UD 261 CHAPTER 13 SERIAL INTERFACE CSI10 Figure 13-1. Block Diagram of Serial Interface CSI10 Internal bus 8 SI10/P11(/RxD0Note) Serial I/O shift register 10 (SIO10) 8 Transmit buffer register 10 (SOTB10) Output selector SO10/P12 Transmit data controller Output latch Output latch (P12) PM12 Transmit controller fX/2 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 SCK10/P10 (/TxD0Note) Selector Clock start/stop controller & clock phase controller INTCSI10 Note PD780102, 780103, 78F0103 only. (1) Transmit buffer register 10 (SOTB10) This register sets the transmit data. Transmission/reception is started by writing data to SOTB10 when bit 7 (CSIE10) and bit 6 (TRMD10) of serial operation mode register 10 (CSIM10) are 1. The data written to SOTB10 is converted from parallel data into serial data by serial I/O shift register 10, and output to the serial output pin (SO10). SOTB10 can be written or read by an 8-bit memory manipulation instruction. RESET input makes this register undefined. Caution Do not access SOTB10 when CSOT10 = 1 (during serial communication). (2) Serial I/O shift register 10 (SIO10) This is an 8-bit register that converts data from parallel data into serial data and vice versa. This register can be read by an 8-bit memory manipulation instruction. Reception is started by reading data from SIO10 if bit 6 (TRMD10) of serial operation mode register 10 (CSIM10) is 0. During reception, the data is read from the serial input pin (SI10) to SIO10. RESET input clears this register to 00H. Caution Do not access SIO10 when CSOT10 = 1 (during serial communication). 262 User's Manual U15836EJ4V0UD CHAPTER 13 SERIAL INTERFACE CSI10 13.3 Registers Controlling Serial Interface CSI10 Serial interface CSI10 is controlled by the following four registers. * Serial operation mode register 10 (CSIM10) * Serial clock selection register 10 (CSIC10) * Port mode register 1 (PM1) * Port register 1 (P1) (1) Serial operation mode register 10 (CSIM10) CSIM10 is used to select the operation mode and enable or disable operation. CSIM10 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 13-2. Format of Serial Operation Mode Register 10 (CSIM10) Address: FF80H After reset: 00H R/W Symbol CSIM10 <7> CSIE10 6 TRMD10 Note 1 5 0 4 DIR10 3 0 2 0 1 0 0 CSOT10 CSIE10 0 1 Disables operation Enables operation Note 2 Operation control in 3-wire serial I/O mode and asynchronously resets the internal circuit Note 3 . TRMD10 0 Note 5 Note 4 Transmit/receive mode control Receive mode (transmission disabled). Transmit/receive mode 1 DIR10 0 1 Note 6 First bit specification MSB LSB CSOT10 0 1 Communication is stopped. Communication is in progress. Communication status flag Notes 1. 2. 3. 4. 5. 6. 7. Bit 0 is a read-only bit. When using P10/SCK10(/TxD0Note 7), P11/SI10(/RxD0Note 7), or P12/SO10 as a general-purpose port, see CHAPTER 4 PORT FUNTIONS and Caution 3 of Figure 13-3. Bit 0 (CSOT10) of CSIM10 and serial I/O shift register 10 (SIO10) are reset. Do not rewrite TRMD10 when CSOT10 = 1 (during serial communication). The SO10 output is fixed to the low level when TRMD10 is 0. Reception is started when data is read from SIO10. Do not rewrite DIR10 when CSOT10 = 1 (during serial communication). PD780102, 780103, and 78F0103 only. Caution Be sure to clear bit 5 to 0. User's Manual U15836EJ4V0UD 263 CHAPTER 13 SERIAL INTERFACE CSI10 (2) Serial clock selection register 10 (CSIC10) This register specifies the timing of the data transmission/reception and sets the serial clock. CSIC10 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 13-3. Format of Serial Clock Selection Register 10 (CSIC10) Address: FF81H After reset: 00H R/W Symbol CSIC10 7 0 6 0 5 0 4 CKP10 3 DAP10 2 CKS102 1 CKS101 0 CKS100 CKP10 0 DAP10 0 Specification of data transmission/reception timing Type 1 SCK10 SO10 SI10 input timing D7 D6 D5 D4 D3 D2 D1 D0 0 1 SCK10 SO10 SI10 input timing D7 D6 D5 D4 D3 D2 D1 D0 2 1 0 SCK10 SO10 SI10 input timing D7 D6 D5 D4 D3 D2 D1 D0 3 1 1 SCK10 SO10 SI10 input timing D7 D6 D5 D4 D3 D2 D1 D0 4 CKS102 0 0 0 0 1 1 1 1 CKS101 0 0 1 1 0 0 1 1 CKS100 0 1 0 1 0 1 0 1 fX/2 (5 MHz) CSI10 serial clock selection Mode Master mode Master mode Master mode Master mode Master mode Master mode Master mode Slave mode fX/2 (2.5 MHz) fX/2 (1.25 MHz) fX/2 (625 kHz) fX/2 (312.5 kHz) fX/2 (156.25 kHz) fX/2 (78.13 kHz) External clock input to SCK10 7 6 5 4 3 2 Cautions 1. When the Ring-OSC clock is selected as the clock supplied to the CPU, the clock of the RingOSC oscillator is divided and supplied as the serial clock. At this time, the operation of serial interface CSI10 is not guaranteed. 2. Do not write to CSIC10 while CSIE10 = 1 (operation enabled). 3. Clear CKP10 to 0 to use P10/SCK10(/TxD0Note) as general-purpose port pins. 4. The phase type of the data clock is type 1 after reset. Note PD780102, 780103, 78F0103 only. 264 User's Manual U15836EJ4V0UD CHAPTER 13 SERIAL INTERFACE CSI10 Remarks 1. Figures in parentheses are for operation with fX = 10 MHz 2. fX: X1 input clock oscillation frequency (3) Port mode register 1 (PM1) This register sets port 1 input/output in 1-bit units. When using P10/SCK10(/TxD0Note) as the clock output pins of the serial interface, and P12/SO10 as the data output pins, clear PM10, PM12, and the output latches of P10, and P12 to 0. When using P10/SCK10(/TxD0Note) as the clock input pins of the serial interface, and P11/SI10(/RxD0Note) as the data input pins, set PM10 and PM11 to 1. At this time, the output latches of P10 and P11 may be 0 or 1. PM1 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to FFH. Note PD780102, 780103, 78F0103 only. Figure 13-4. Format of Port Mode Register 1 (PM1) Address: FF21H Symbol PM1 7 PM17 After reset: FFH 6 PM16 R/W 5 PM15 4 PM14 3 PM13 2 PM12 1 PM11 0 PM10 PM1n 0 1 P1n pin I/O mode selection (n = 0 to 7) Output mode (output buffer on) Input mode (output buffer off) User's Manual U15836EJ4V0UD 265 CHAPTER 13 SERIAL INTERFACE CSI10 13.4 Operation of Serial Interface CSI10 Serial interface CSI10 can be used in the following two modes. * Operation stop mode * 3-wire serial I/O mode 13.4.1 Operation stop mode Serial communication is not executed in this mode. Therefore, the power consumption can be reduced. In addition, the P10/SCK10(/TXD0Note), P11/SI10(/RXD0Note), and P12/SO10 pins can be used as ordinary I/O port pins in this mode. Note PD780102, 780103, and 78F0103 only. (1) Register used The operation stop mode is set by serial operation mode register 10 (CSIM10). To set the operation stop mode, clear bit 7 (CSIE10) of CSIM10 to 0. (a) Serial operation mode register 10 (CSIM10) CSIM10 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM10 to 00H. Address: FF80H After reset: 00H R/W Symbol CSIM10 <7> CSIE10 6 TRMD10 5 0 4 DIR10 3 0 2 0 1 0 0 CSOT10 CSIE10 0 Disables operation Note 1 Operation control in 3-wire serial I/O mode and asynchronously resets the internal circuit Note 2 . Notes 1. 2. 3. When using P10/SCK10(/TxD0Note 3), P11/SI10(RxD0Note 3), or P12/SO10 as general-purpose port pins, see CHAPTER 4 PORT FUNCTIONS and Caution 3 of Figure 13-3. Bit 0 (CSOT10) of CSIM10 and serial I/O shift register 10 (SIO10) are reset. PD780102, 780103, and 78F0103 only. 266 User's Manual U15836EJ4V0UD CHAPTER 13 SERIAL INTERFACE CSI10 13.4.2 3-wire serial I/O mode The 3-wire serial I/O mode can be used for connecting peripheral ICs and display controllers that have a clocked serial interface. In this mode, communication is executed by using three lines: the serial clock (SCK10), serial output (SO10), and serial input (SI10) lines. (1) Registers used * Serial operation mode register 10 (CSIM10) * Serial clock selection register 10 (CSIC10) * Port mode register 1 (PM1) * Port register 1 (P1) The basic procedure of setting an operation in the 3-wire serial I/O mode is as follows. <1> Set the CSIC10 register (see Figure 13-3). <2> Set bits 0, 4, and 6 (CSOT10, DIR10, and TRMD10) of the CSIM10 register (see Figure 13-2). <3> Set bit 7 (CSIE10) of the CSIM10 register to 1. Transmission/reception is enabled. <4> Write data to transmit buffer register 10 (SOTB10). Data transmission/reception is started. Read data from serial I/O shift register 10 (SIO10). Data reception is started. Caution Take relationship with the other party of communication when setting the port mode register and port register. User's Manual U15836EJ4V0UD 267 CHAPTER 13 SERIAL INTERFACE CSI10 The relationship between the register settings and pins is shown below. Table 13-2. Relationship Between Register Settings and Pins CSIE10 TRMD10 PM11 P11 PM12 P12 PM10 P10 CSI10 Operation P11/SI10 (/RxD0 0 x x Note 1 Note 4 Pin Function P12/SO10 ) P12 ) P12 P10/SCK10 (/TxD0 Note 4 ) x Note 1 x Note 1 x Note 1 x Note 1 x Note 1 Stop P11 (/RxD0 Note 4 P10 (/TxD0 Note4 Note2 ) 1 0 1 Note 1 x Note 1 x Note 1 x Note 1 1 x Slave reception Note 3 SI10 SCK10 (input) Note 3 1 1 x x 0 0 1 x Slave transmission Note 3 P11 (/RxD0 Note 4 SO10 ) SO10 SCK10 (input) Note 3 1 1 1 x 0 0 1 x Slave transmission/ reception Note 3 SI10 SCK10 (input) Note 3 1 0 1 Note 1 x Note 1 x Note 1 x Note 1 0 1 Master reception SI10 P12 SCK10 (output) 1 1 x x 0 0 0 1 Master transmission P11 (/RxD0 Note 4 SO10 ) SO10 SCK10 (output) SCK10 (output) 1 1 1 x 0 0 0 1 Master transmission/ reception SI10 Notes 1. Can be set as port function. 2. To use P10/SCK10(/TxD0Note 4) as port pins, clear CKP10 to 0. 3. To use the slave mode, set CKS102, CKS101, and CKS100 to 1, 1, 1. 4. PD780102, 780103, and 78F0103 only. Remark x: CSIE10: TRMD10: CKP10: PM1x: P1x: don't care Bit 7 of serial operation mode register 10 (CSIM10) Bit 6 of CSIM10 Bit 4 of serial clock selection register 10 (CSIC10) Port mode register Port output latch CKS102, CKS101, CKS100: Bits 2 to 0 of CSIC10 268 User's Manual U15836EJ4V0UD CHAPTER 13 SERIAL INTERFACE CSI10 (2) Communication operation In the 3-wire serial I/O mode, data is transmitted or received in 8-bit units. Each bit of the data is transmitted or received in synchronization with the serial clock. Data can be transmitted or received if bit 6 (TRMD10) of serial operation mode register 10 (CSIM10) is 1. Transmission/reception is started when a value is written to transmit buffer register 10 (SOTB10). In addition, data can be received when bit 6 (TRMD10) of serial operation mode register 10 (CSIM10) is 0. Reception is started when data is read from serial I/O shift register 10 (SIO10). After communication has been started, bit 0 (CSOT10) of CSIM10 is set to 1. When communication of 8-bit data has been completed, a communication completion interrupt request flag (CSIIF10) is set, and CSOT10 is cleared to 0. Then the next communication is enabled. Caution Do not access the control register and data register when CSOT10 = 1 (during serial communication). Figure 13-5. Timing in 3-Wire Serial I/O Mode (1/2) (1) Transmission/reception timing (Type 1; TRMD10 = 1, DIR10 = 0, CKP10 = 0, DAP10 = 0) SCK10 Read/write trigger SOTB10 55H (communication data) SIO10 ABH 56H ADH 5AH B5H 6AH D5H AAH CSOT10 INTCSI10 CSIIF10 SI10 (receive AAH) SO10 55H is written to SOTB10. User's Manual U15836EJ4V0UD 269 CHAPTER 13 SERIAL INTERFACE CSI10 Figure 13-5. Timing in 3-Wire Serial I/O Mode (2/2) (2) Transmission/reception timing (Type 2; TRMD10 = 1, DIR10 = 0, CKP10 = 0, DAP10 = 1) SCK10 Read/write trigger SOTB10 55H (communication data) SIO10 ABH 56H ADH 5AH B5H 6AH D5H AAH CSOT10 INTCSI10 CSIIF10 SI10 (input AAH) SO10 55H is written to SOTB10. 270 User's Manual U15836EJ4V0UD CHAPTER 13 SERIAL INTERFACE CSI10 Figure 13-6. Timing of Clock/Data Phase (a) Type 1; CKP10 = 0, DAP10 = 0 SCK10 SI10 capture SO10 Writing to SOTB10 or reading from SIO10 CSIIF10 CSOT10 D7 D6 D5 D4 D3 D2 D1 D0 (b) Type 2; CKP10 = 0, DAP10 = 1 SCK10 SI10 capture SO10 Writing to SOTB10 or reading from SIO10 CSIIF10 CSOT10 D7 D6 D5 D4 D3 D2 D1 D0 (c) Type 3; CKP10 = 1, DAP10 = 0 SCK10 SI10 capture SO10 Writing to SOTB10 or reading from SIO10 CSIIF10 CSOT10 D7 D6 D5 D4 D3 D2 D1 D0 (d) Type 4; CKP10 = 1, DAP10 = 1 SCK10 SI10 capture SO10 Writing to SOTB10 or reading from SIO10 CSIIF10 CSOT10 D7 D6 D5 D4 D3 D2 D1 D0 User's Manual U15836EJ4V0UD 271 CHAPTER 13 SERIAL INTERFACE CSI10 (3) Timing of output to SO10 pin (first bit) When communication is started, the value of transmit buffer register 10 (SOTB10) is output from the SO10 pin. The output operation of the first bit at this time is described below. Figure 13-7. Output Operation of First Bit (1) When CKP10 = 0, DAP10 = 0 (or CKP10 = 1, DAP10 = 0) SCK10 Writing to SOTB10 or reading from SIO10 SOTB10 SIO10 Output latch SO10 First bit 2nd bit The first bit is directly latched by the SOTB10 register to the output latch at the falling (or rising) edge of SCK10, and output from the SO10 pin via an output selector. Then, the value of the SOTB10 register is transferred to the SIO10 register at the next rising (or falling) edge of SCK10, and shifted one bit. At the same time, the first bit of the receive data is stored in the SIO10 register via the SI10 pin. The second and subsequent bits are latched by the SIO10 register to the output latch at the next falling (or rising) edge of SCK10, and the data is output from the SO10 pin. (2) When CKP10 = 0, DAP10 = 1 (or CKP10 = 1, DAP10 = 1) SCK10 Writing to SOTB10 or reading from SIO10 SOTB10 SIO10 Output latch SO10 First bit 2nd bit 3rd bit The first bit is directly latched by the SOTB10 register at the falling edge of the write signal of the SOTB10 register or the read signal of the SIO10 register, and output from the SO10 pin via an output selector. Then, the value of the SOTB10 register is transferred to the SIO10 register at the next falling (or rising) edge of SCK10, and shifted one bit. At the same time, the first bit of the receive data is stored in the SIO10 register via the SI10 pin. The second and subsequent bits are latched by the SIO10 register to the output latch at the next rising (or falling) edge of SCK10, and the data is output from the SO10 pin. 272 User's Manual U15836EJ4V0UD CHAPTER 13 SERIAL INTERFACE CSI10 (4) Output value of SO10 pin (last bit) After communication has been completed, the SO10 pin holds the output value of the last bit. Figure 13-8. Output Value of SO10 Pin (Last Bit) (1) Type 1; when CKP10 = 0 and DAP10 = 0 (or CKP10 = 1, DAP10 = 0) SCK10 Writing to SOTB10 or reading from SIO10 SOTB10 SIO10 Output latch SO10 Last bit ( Next request is issued.) (2) Type 2; when CKP10 = 0 and DAP10 = 1 (or CKP10 = 1, DAP10 = 1) SCK10 Writing to SOTB10 or reading from SIO10 SOTB10 SIO10 Output latch SO10 Last bit ( Next request is issued.) User's Manual U15836EJ4V0UD 273 CHAPTER 13 SERIAL INTERFACE CSI10 (5) SO10 output The status of the SO10 output is as follows if bit 7 (CSIE10) of serial operation mode register 10 (CSIM10) is cleared to 0. Table 13-3. SO10 Output Status TRMD10 TRMD10 = 0 TRMD10 = 1 Note DAP10 - DAP10 = 0 DIR10 - - DIR10 = 0 DIR10 = 1 SO10 Output Outputs low level Note . Value of SO10 latch (low-level output) DAP10 = 1 Value of bit 7 of SOTB10 Value of bit 0 of SOTB10 Note Status after reset Caution If a value is written to TRMD10, DAP10, and DIR10, the output value of SO10 changes. 274 User's Manual U15836EJ4V0UD CHAPTER 14 INTERRUPT FUNCTIONS 14.1 Interrupt Function Types The following two types of interrupt functions are used. (1) Maskable interrupts These interrupts undergo mask control. Maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specification flag registers (PR0L, PR0H, PR1L). Multiple interrupt servicing of high-priority interrupts can be applied to low priority interrupts. If two or more interrupts with the same priority are simultaneously generated, each interrupt is serviced according to its predetermined priority (see Table 14-1). A standby release signal is generated and the STOP mode and HALT mode are released by maskable interrupts. Six external interrupt requests and 12 internal interrupt requests are provided as maskable interrupts. (2) Software interrupt This is a vectored interrupt generated by executing the BRK instruction. It is acknowledged even when interrupts are disabled. The software interrupt does not undergo interrupt priority control. 14.2 Interrupt Sources and Configuration A total of 19 interrupt sources exist for maskable and software interrupts. In addition, maximum total of 5 reset sources are also provided (see Table 14-1). User's Manual U15836EJ4V0UD 275 CHAPTER 14 INTERRUPT FUNCTIONS Table 14-1. Interrupt Source List Interrupt Type Default Priority Note 1 Interrupt Source Name INTLVI INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTSRE6 INTSR6 INTST6 INTCSI10/ INTST0 Note 4 Internal/ External Vector Table Address Basic Configuration Type (A) (B) Note 2 Trigger Low-voltage detection Note 3 Maskable 0 1 2 3 4 5 6 7 8 9 10 Internal External 0004H 0006H 0008H 000AH 000CH 000EH 0010H Pin input edge detection UART6 reception error generation End of UART6 reception End of UART6 transmission End of CSI10 communication/end of UART0 transmission Match between TMH1 and CRH1 (when compare register is specified) Internal 0012H 0014H 0016H 0018H (A) 11 INTTMH1 001AH 12 INTTMH0 Match between TMH0 and CRH0 (when compare register is specified) 001CH 13 INTTM50 Match between TM50 and CR50 (when compare register is specified) 001EH 14 INTTM000 Match between TM00 and CR000 (when compare register is specified) 0020H 15 INTTM010 Match between TM00 and CR010 (when compare register is specified) 0022H 16 17 Software Reset - - INTAD INTSR0 BRK RESET POC LVI Clock monitor WDT Note 4 End of A/D conversion End of UART0 reception BRK instruction execution Reset input Power-on-clear Note 5 0024H 0026H - - 003EH 0000H (C) - Low-voltage detection Note 6 X1 input clock stop detection WDT overflow Notes 1. 2. 3. 4. 5. 6. The default priority is the priority applicable when two or more maskable interrupt are generated simultaneously. 0 is the highest priority, and 17 is the lowest. Basic configuration types (A) to (C) correspond to (A) to (C) in Figure 14-1. When bit 1 (LVIMD) = 0 is selected for the low-voltage detection register (LVIM). The interrupt sources INTST0 and INTSR0 are available only in the PD780102, 780103, and 78F0103. When "POC used" is selected by mask option. When LVIMD = 1 is selected. 276 User's Manual U15836EJ4V0UD CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-1. Basic Configuration of Interrupt Function (A) Internal maskable interrupt Internal bus MK IE PR ISP Interrupt request IF Priority controller Vector table address generator Standby release signal (B) External maskable interrupt (INTP0 to INTP5) Internal bus External interrupt edge enable register (EGP, EGN) MK IE PR ISP Interrupt request Edge detector IF Priority controller Vector table address generator Standby release signal (C) Software interrupt Internal bus Interrupt request Priority controller Vector table address generator IF: IE: ISP: MK: PR: Interrupt request flag Interrupt enable flag In-service priority flag Interrupt mask flag Priority specification flag User's Manual U15836EJ4V0UD 277 CHAPTER 14 INTERRUPT FUNCTIONS 14.3 Registers Controlling Interrupt Function The following 6 types of registers are used to control the interrupt functions. * Interrupt request flag register (IF0L, IF0H, IF1L) * Interrupt mask flag register (MK0L, MK0H, MK1L) * Priority specification flag register (PR0L, PR0H, PR1L) * External interrupt rising edge enable register (EGP) * External interrupt falling edge enable register (EGN) * Program status word (PSW) Table 14-2 shows a list of interrupt request flags, interrupt mask flags, and priority specification flags corresponding to interrupt request sources. Table 14-2. Flags Corresponding to Interrupt Request Sources Interrupt Request INTLVI INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTSRE6 INTSR6 INTST6 INTST0 Note 1 Interrupt Request Flag Register LVIIF PIF0 PIF1 PIF2 PIF3 PIF4 PIF5 SREIF6 SRIF6 STIF6 DUALIF0 CSIIF10 TMIFH1 TMIFH0 TMIF50 TMIF000 TMIF010 ADIF IF1L Note 1 Note 2 Interrupt Mask Flag Register LVIMK PMK0 PMK1 PMK2 PMK3 PMK4 PMK5 SREMK6 MK0L Priority Specification Flag Register LVIPR PPR0 PPR1 PPR2 PPR3 PPR4 PPR5 SREPR6 PR0L IF0L IF0H SRMK6 STMK6 DUALMK0 CSIMK10 TMMKH1 TMMKH0 TMMK50 TMMK000 TMMK010 ADMK SRMK0 Note 1 Note 4 MK0H SRPR6 STPR6 DUALPR0 CSIPR10 TMPRH1 TMPRH0 TMPR50 TMPR000 TMPR010 Note 4 PR0H INTCSI10 INTTMH1 INTTMH0 INTTM50 INTTM000 INTTM010 INTAD INTSR0 Note 1 Note 3 Note 3 Note 3 MK1L ADPR SRPR0 Note 1 PR1L SRIF0 Notes 1. 2. 3. 4. PD780102, 780103, and 78F0103 only. Flag name in the PD780102, 780103, and 78F0103. If either of the two types of interrupt sources is generated, these flags are set (1). Flag name in the PD780101 These are the flag names in the PD780102, 780103, and 78F0103. These flags support two types of interrupt sources. 278 User's Manual U15836EJ4V0UD CHAPTER 14 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H, IF1L) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of RESET input. When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt routine is entered. IF0L, IF0H, and IF1L are set by a 1-bit or 8-bit memory manipulation instruction. When IF0L and IF0H are combined to form 16-bit register IF0, they are read with a 16-bit memory manipulation instruction. RESET input sets these registers to 00H. Figure 14-2. Format of Interrupt Request Flag Register (IF0L, IF0H, IF1L) Address: FFE0H After reset: 00H R/W Symbol IF0L <7> SREIF6 <6> PIF5 <5> PIF4 <4> PIF3 <3> PIF2 <2> PIF1 <1> PIF0 <0> LVIIF Address: FFE1H Symbol IF0H After reset: 00H <7> <6> TMIF000 R/W <5> TMIF50 <4> TMIFH0 <3> TMIFH1 <2> DUALIF0 Note 1 <1> STIF6 <0> SRIF6 TMIF010 Address: FFE2H Symbol IF1L After reset: 00H 7 0 6 0 R/W 5 0 4 0 3 0 2 0 <1> SRIF0 Note 2 <0> ADIF XXIFX 0 1 Interrupt request flag No interrupt request signal is generated Interrupt request is generated, interrupt request status Notes 1. 2. This is CSIIF10 in the PD780101. PD780102, 780103, and 78F0103 only. Cautions 1. Be sure to set bits 2 to 7 of IF1L to 0. 2. When operating a timer, serial interface, or A/D converter after standby release, operate it once after clearing the interrupt request flag. An interrupt request flag may be set by noise. 3. If an interrupt request corresponding to a flag of the interrupt request flag register is generated while the interrupt request flag register is being manipulated (including by 1-bit memory manipulation), the flag corresponding to the interrupt request may not be set to 1. User's Manual U15836EJ4V0UD 279 CHAPTER 14 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers (MK0L, MK0H, MK1L) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. MK0L, MK0H, and MK1L are set by a 1-bit or 8-bit memory manipulation instruction. When MK0L and MK0H are combined to form a 16-bit register MK0, they are set with a 16-bit memory manipulation instruction. RESET input sets these registers to FFH. Figure 14-3. Format of Interrupt Mask Flag Register (MK0L, MK0H, MK1L) Address: FFE4H Symbol MK0L After reset: FFH <7> SREMK6 <6> PMK5 R/W <5> PMK4 <4> PMK3 <3> PMK2 <2> PMK1 <1> PMK0 <0> LVIMK Address: FFE5H Symbol MK0H After reset: FFH <7> <6> TMMK000 R/W <5> TMMK50 <4> TMMKH0 <3> TMMKH1 <2> DUALMK0 Note 1 <1> STMK6 <0> SRMK6 TMMK010 Address: FFE6H Symbol MK1L After reset: FFH 7 1 6 1 R/W 5 1 4 1 3 1 2 1 <1> SRMK0 Note 2 <0> ADMK XXMKX 0 1 Interrupt servicing enabled Interrupt servicing disabled Interrupt servicing control Notes 1. 2. This is CSIMK10 in the PD780101. PD780102, 780103, and 78F0103 only. Caution Be sure to set bits 2 to 7 of MK1L to 1. 280 User's Manual U15836EJ4V0UD CHAPTER 14 INTERRUPT FUNCTIONS (3) Priority specification flag registers (PR0L, PR0H, PR1L) The priority specification flag registers are used to set the corresponding maskable interrupt priority order. PR0L, PR0H, and PR1L are set by a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are combined to form 16-bit register PR0, they are set with a 16-bit memory manipulation instruction. RESET input sets these registers to FFH. Figure 14-4. Format of Priority Specification Flag Register (PR0L, PR0H, PR1L) Address: FFE8H Symbol PR0L After reset: FFH <7> SREPR6 <6> PPR5 R/W <5> PPR4 <4> PPR3 <3> PPR2 <2> PPR1 <1> PPR0 <0> LVIPR Address: FFE9H Symbol PR0H After reset: FFH <7> <6> TMPR000 R/W <5> TMPR50 <4> TMPRH0 <3> TMPRH1 <2> DUALPR0 Note1 <1> STPR6 <0> SRPR6 TMPR010 Address: FFEAH Symbol PR1L After reset: FFH 7 1 6 1 R/W 5 1 4 1 3 1 2 1 <1> SRPR0 Note 2 <0> ADPR XXPRX 0 1 High priority level Low priority level Priority level selection Notes 1. 2. This is CSIPRI0 in the PD780101. PD780102, 780103, and 78F0103 only. Caution Be sure to set bits 2 to 7 of PR1L to 1. User's Manual U15836EJ4V0UD 281 CHAPTER 14 INTERRUPT FUNCTIONS (4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN) These registers specify the valid edge for INTP0 to INTP5. EGP and EGN are set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears these registers to 00H. Figure 14-5. Format of External Interrupt Rising Edge Enable Register (EGP) and External Interrupt Falling Edge Enable Register (EGN) Address: FF48H Symbol EGP After reset: 00H 7 0 6 0 R/W 5 EGP5 4 EGP4 3 EGP3 2 EGP2 1 EGP1 0 EGP0 Address: FF49H Symbol EGN After reset: 00H 7 0 6 0 R/W 5 EGN5 4 EGN4 3 EGN3 2 EGN2 1 EGN1 0 EGN0 EGPn 0 0 1 1 EGNn 0 1 0 1 INTPn pin valid edge selection (n = 0 to 5) Edge detection disabled Falling edge Rising edge Both rising and falling edges Table 14-3 shows the ports corresponding to EGPn and EGNn. Table 14-3. Ports Corresponding to EGPn and EGNn Detection Enable Register EGP0 EGP1 EGP2 EGP3 EGP4 EGP5 EGN0 EGN1 EGN2 EGN3 EGN4 EGN5 P120 P30 P31 P32 P33 P16 Edge Detection Port Interrupt Request Signal INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 Caution Select the port mode by clearing EGPn and EGNn to 0 because an edge may be detected when the external interrupt function is switched to the port function. Remark n = 0 to 5 282 User's Manual U15836EJ4V0UD CHAPTER 14 INTERRUPT FUNCTIONS (5) Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for an interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP flag that controls multiple interrupt servicing are mapped to the PSW. Besides 8-bit read/write, this register can carry out operations using bit manipulation instructions and dedicated instructions (EI and DI). When a vectored interrupt request is acknowledged, if the BRK instruction is executed, the contents of the PSW are automatically saved into a stack and the IE flag is reset to 0. If a maskable interrupt request is acknowledged, the contents of the priority specification flag of the acknowledged interrupt are transferred to the ISP flag. The PSW contents are also saved into the stack with the PUSH PSW instruction. They are restored from the stack with the RETI, RETB, and POP PSW instructions. RESET input sets PSW to 02H. Figure 14-6. Format of Program Status Word <7> PSW IE <6> Z <5> RBS1 <4> AC <3> RBS0 2 0 <1> ISP 0 CY After reset 02H Used when normal instruction is executed ISP 0 Priority of interrupt currently being serviced High-priority interrupt servicing (low-priority interrupt disabled) Interrupt request not acknowledged, or lowpriority interrupt servicing (all maskable interrupts enabled) 1 IE 0 1 Interrupt request acknowledgment enable/disable Disabled Enabled User's Manual U15836EJ4V0UD 283 CHAPTER 14 INTERRUPT FUNCTIONS 14.4 Interrupt Servicing Operations 14.4.1 Maskable interrupt request acknowledgment A maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the IE flag is set to 1). However, a low-priority interrupt request is not acknowledged during servicing of a higher priority interrupt request (when the ISP flag is reset to 0). The times from generation of a maskable interrupt request until interrupt servicing is performed are listed in Table 14-4 below. For the interrupt request acknowledgment timing, see Figures 14-8 and 14-9. Table 14-4. Time from Generation of Maskable Interrupt Request Until Servicing Minimum Time When xxPR = 0 When xxPR = 1 7 clocks 8 clocks Maximum Time 32 clocks 33 clocks Note Note If an interrupt request is generated just before a divide instruction, the wait time becomes longer. Remark 1 clock: 1/fCPU (fCPU: CPU clock) If two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level specified in the priority specification flag is acknowledged first. If two or more interrupt requests have the same priority level, the request with the highest default priority is acknowledged first. An interrupt request that is held pending is acknowledged when it becomes acknowledgeable. Figure 14-7 shows the interrupt request acknowledgment algorithm. If a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW, then PC, the IE flag is reset (0), and the contents of the priority specification flag corresponding to the acknowledged interrupt are transferred to the ISP flag. The vector table data determined for each interrupt request is loaded into the PC and branched. Restoring from an interrupt is possible by using the RETI instruction. 284 User's Manual U15836EJ4V0UD CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-7. Interrupt Request Acknowledgment Processing Algorithm Start No xxIF = 1? Yes (interrupt request generation) No xxMK = 0? Yes Interrupt request held pending Yes (High priority) xxPR = 0? No (Low priority) Yes Any high-priority interrupt request among those simultaneously generated with xxPR = 0? Interrupt request held pending No No IE = 1? Yes Any high-priority interrupt request among those simultaneously generated with xxPR = 0? Yes No Any high-priority interrupt request among those simultaneously generated? Interrupt request held pending Yes Interrupt request held pending No Vectored interrupt servicing IE = 1? Yes ISP = 1? Yes Interrupt request held pending No Interrupt request held pending No Interrupt request held pending Vectored interrupt servicing xxIF: Interrupt request flag xxMK: Interrupt mask flag xxPR: Priority specification flag IE: ISP: Flag that controls acknowledgment of maskable interrupt request (1 = Enable, 0 = Disable) Flag that indicates the priority level of the interrupt currently being serviced (0 = High-priority interrupt servicing, 1 = No interrupt request acknowledged, or low-priority interrupt servicing) User's Manual U15836EJ4V0UD 285 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-8. Interrupt Request Acknowledgment Timing (Minimum Time) 6 clocks CPU processing xxIF (xxPR = 1) 8 clocks xxIF (xxPR = 0) 7 clocks Instruction Instruction PSW and PC saved, jump to interrupt servicing Interrupt servicing program Remark 1 clock: 1/fCPU (fCPU: CPU clock) Figure 14-9. Interrupt Request Acknowledgment Timing (Maximum Time) 25 clocks 6 clocks PSW and PC saved, jump to interrupt servicing CPU processing xxIF (xxPR = 1) Instruction Divide instruction Interrupt servicing program 33 clocks xxIF (xxPR = 0) 32 clocks Remark 1 clock: 1/fCPU (fCPU: CPU clock) 14.4.2 Software interrupt request acknowledgment A software interrupt request is acknowledged by BRK instruction execution. disabled. If a software interrupt request is acknowledged, the contents are saved into the stacks in the order of the program status word (PSW), then program counter (PC), the IE flag is reset (0), and the contents of the vector table (003EH, 003FH) are loaded into the PC and branched. Restoring from a software interrupt is possible by using the RETB instruction. Caution Do not use the RETI instruction for restoring from the software interrupt. Software interrupts cannot be 286 User's Manual U15836EJ4V0UD CHAPTER 14 INTERRUPT FUNCTIONS 14.4.3 Multiple interrupt servicing Multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt. Multiple interrupt servicing does not occur unless the interrupt request acknowledgment enabled state is selected (IE = 1). When an interrupt request is acknowledged, interrupt request acknowledgment becomes disabled (IE = 0). Therefore, to enable multiple interrupt servicing, it is necessary to set (1) the IE flag with the EI instruction during interrupt servicing to enable interrupt acknowledgment. Moreover, even if interrupts are enabled, multiple interrupt servicing may not be enabled, this being subject to interrupt priority control. Two types of priority control are available: default priority control and programmable priority control. Programmable priority control is used for multiple interrupt servicing. In the interrupt enabled state, if an interrupt request with a priority equal to or higher than that of the interrupt currently being serviced is generated, it is acknowledged for multiple interrupt servicing. If an interrupt with a priority lower than that of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged for multiple interrupt servicing. Interrupt requests that are not enabled because interrupts are in the interrupt disabled state or because they have a lower priority are held pending. When servicing of the current interrupt ends, the pending interrupt request is acknowledged following execution of at least one main processing instruction execution. Table 14-5 shows relationship between interrupt requests enabled for multiple interrupt servicing and Figure 14-10 shows multiple interrupt servicing examples. Table 14-5. Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing During Interrupt Servicing Multiple Interrupt Request Maskable Interrupt Request PR = 0 Interrupt Being Serviced Maskable interrupt ISP = 0 ISP = 1 Software interrupt IE = 1 IE = 0 x x x IE = 1 x PR = 1 IE = 0 x x x Software Interrupt Request Remarks 1. : Multiple interrupt servicing enabled 2. x: Multiple interrupt servicing disabled 3. The ISP and IE are flags contained in the PSW. ISP = 0: An interrupt with higher priority is being serviced. ISP = 1: No interrupt request has been acknowledged, or an interrupt with a lower priority is being serviced. IE = 0: IE = 1: Interrupt request acknowledgment is disabled. Interrupt request acknowledgment is enabled. 4. PR is a flag contained in PR0L, PR0H, and PR1L. PR = 0: Higher priority level PR = 1: Lower priority level User's Manual U15836EJ4V0UD 287 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-10. Examples of Multiple Interrupt Servicing (1/2) Example 1. Multiple interrupt servicing occurs twice Main processing INTxx servicing INTyy servicing INTzz servicing EI IE = 0 EI INTyy (PR = 0) IE = 0 EI INTzz (PR = 0) IE = 0 INTxx (PR = 1) RETI IE = 1 IE = 1 RETI IE = 1 RETI During servicing of interrupt INTxx, two interrupt requests, INTyy and INTzz, are acknowledged, and multiple interrupt servicing takes place. Before each interrupt request is acknowledged, the EI instruction must always be issued to enable interrupt request acknowledgment. Example 2. Multiple interrupt servicing does not occur due to priority control Main processing INTxx servicing INTyy servicing EI IE = 0 EI INTxx (PR = 0) INTyy (PR = 1) IE = 1 RETI 1 instruction execution IE = 0 RETI IE = 1 Interrupt request INTyy issued during servicing of interrupt INTxx is not acknowledged because its priority is lower than that of INTxx, and multiple interrupt servicing does not take place. The INTyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. PR = 0: Higher priority level PR = 1: Lower priority level IE = 0: Interrupt request acknowledgment disabled 288 User's Manual U15836EJ4V0UD CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-10. Examples of Multiple Interrupt Servicing (2/2) Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled Main processing IE = 0 EI INTyy (PR = 0) RETI IE = 1 INTxx servicing INTyy servicing INTxx (PR = 0) 1 instruction execution IE = 0 RETI IE = 1 Interrupts are not enabled during servicing of interrupt INTxx (EI instruction is not issued), therefore, interrupt request INTyy is not acknowledged and multiple interrupt servicing does not take place. The INTyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. PR = 0: Higher priority level IE = 0: Interrupt request acknowledgment disabled User's Manual U15836EJ4V0UD 289 CHAPTER 14 INTERRUPT FUNCTIONS 14.4.4 Interrupt request hold There are instructions where, even if an interrupt request is issued for them while another instruction is being executed, request acknowledgment is held pending until the end of execution of the next instruction. instructions (interrupt request hold instructions) are listed below. * MOV PSW, #byte * MOV A, PSW * MOV PSW, A * MOV1 PSW. bit, CY * MOV1 CY, PSW. bit * AND1 CY, PSW. bit * OR1 CY, PSW. bit * XOR1 CY, PSW. bit * SET1 PSW. bit * CLR1 PSW. bit * RETB * RETI * PUSH PSW * POP PSW * BT PSW. bit, $addr16 * BF PSW. bit, $addr16 * BTCLR PSW. bit, $addr16 * EI * DI * Manipulation instructions for the IF0L, IF0H, IF1L, MK0L, MK0H, MK1L, PR0L, PR0H, and PR1L registers Caution The BRK instruction is not one of the above-listed interrupt request hold instructions. However, the software interrupt activated by executing the BRK instruction causes the IE flag to be cleared to 0. Therefore, even if a maskable interrupt request is generated during execution of the BRK instruction, the interrupt request is not acknowledged. Figure 14-11 shows the timing at which interrupt requests are held pending. Figure 14-11. Interrupt Request Hold PSW and PC saved, jump to interrupt servicing Interrupt servicing program These CPU processing Instruction N Instruction M xxIF Remarks 1. Instruction N: Interrupt request hold instruction 2. Instruction M: Instruction other than interrupt request hold instruction 3. The xxPR (priority level) values do not affect the operation of xxIF (interrupt request). 290 User's Manual U15836EJ4V0UD CHAPTER 15 STANDBY FUNCTION 15.1 Standby Function and Configuration 15.1.1 Standby function Table 15-1. Relationship Between Operation Clocks in Each Operation Status Status X1 Oscillator Ring-OSC Oscillator CPU Clock After Operation Mode Reset STOP HALT Oscillating Stopped Note 1 Note 2 RSTOP = 0 Stopped Oscillating Oscillating Stopped RSTOP = 1 Ring-OSC Note 3 Note 4 Stopped Stopped Ring-OSC X1 Release Prescaler Clock Supplied to Peripherals MCM0 = 0 MCM0 = 1 Notes 1. 2. 3. 4. When "Cannot be stopped" is selected for Ring-OSC by a mask option. When "Can be stopped by software" is selected for Ring-OSC by a mask option. Operates using the CPU clock at STOP instruction execution. Operates using the CPU clock at HALT instruction execution. Caution The RSTOP setting is valid only when "Can be stopped by software" is set for Ring-OSC by a mask option. Remark RSTOP: Bit 0 of the Ring-OSC mode register (RCM) MCM0: Bit 0 of the main clock mode register (MCM) The standby function is designed to reduce the operating current consumption of the system. The following two modes are available. User's Manual U15836EJ4V0UD 291 CHAPTER 15 STANDBY FUNCTION (1) HALT mode HALT instruction execution sets the HALT mode. The HALT mode is intended to stop the CPU operation clock. If the X1 input clock and Ring-OSC clock oscillator are operating before the HALT mode is set, oscillation of the X1 input clock and Ring-OSC clock continues. In this mode, operating current is not decreased as much as in the STOP mode. However, the HALT mode is effective for restarting operation immediately upon interrupt request generation and carrying out intermittent operations. (2) STOP mode STOP instruction execution sets the STOP mode. In the STOP mode, the X1 oscillator stops, stopping the whole system, thereby considerably reducing the CPU operating current. Because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out. However, because a wait time is required to secure the oscillation stabilization time after the STOP mode is released, select the HALT mode if it is necessary to start processing immediately upon interrupt request generation. In either of these two modes, all the contents of registers, flags and data memory just before the standby mode is set are held. The I/O port output latches and output buffer statuses are also held. Cautions 1. When shifting to the STOP mode, be sure to stop the peripheral hardware operation before executing STOP instruction. 2. The following sequence is recommended for operating current reduction of the A/D converter when the standby function is used: First clear bit 7 (ADCS) of the A/D converter mode register (ADM) to 0 to stop the A/D conversion operation, and then execute the HALT or STOP instruction. 3. If the Ring-OSC oscillator is operating before the STOP mode is set, oscillation of the RingOSC clock cannot be stopped in the STOP mode. However, when the Ring-OSC clock is used as the CPU clock, operation is stopped for 17/fR (s) after STOP mode is released. 292 User's Manual U15836EJ4V0UD CHAPTER 15 STANDBY FUNCTION 15.1.2 Registers controlling standby function The standby function is controlled by the following two registers. * Oscillation stabilization time counter status register (OSTC) * Oscillation stabilization time select register (OSTS) Remark For the registers that start, stop, or select the clock, see CHAPTER 5 CLOCK GENERATOR. (1) Oscillation stabilization time counter status register (OSTC) This is the status register of the X1 input clock oscillation stabilization time counter. If the Ring-OSC clock is used as the CPU clock, the X1 input clock oscillation stabilization time can be checked. OSTC can be read by a 1-bit or 8-bit memory manipulation instruction. When reset is released (reset by RESET input, POC, LVI, clock monitor, and WDT), the STOP instruction, and MSTOP (bit 7 of MOC register) = 1 clear OSTC to 00H. Figure 15-1. Format of Oscillation Stabilization Time Counter Status Register (OSTC) Address: FFA3H Symbol OSTC After reset: 00H 7 0 6 0 R 5 0 4 MOST11 3 MOST13 2 MOST14 1 MOST15 0 MOST16 MOST11 1 1 1 1 1 MOST13 0 1 1 1 1 MOST14 0 0 1 1 1 MOST15 0 0 0 1 1 MOST16 0 0 0 0 1 Oscillation stabilization time status 2 /fX min. (204.8 s min.) 11 2 /fX min. (819.2 s min.) 13 2 /fX min. (1.64 ms min.) 2 /fX min. (3.27 ms min.) 2 /fX min. (6.55 ms min.) 16 15 14 Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST11 and remain 1. 2. If the STOP mode is entered and then released while the Ring-OSC clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS The X1 oscillation stabilization time counter counts only during the oscillation stabilization time set by OSTS. Therefore, note that only the statuses during the oscillation stabilization time set by OSTS are set to OSTC after STOP mode has been released. 3. The wait time when STOP mode is released does not include the time after STOP mode release until clock oscillation starts ("a" below) regardless of whether STOP mode is released by RESET input or interrupt generation. STOP mode release X1 pin voltage waveform a Remarks 1. Values in parentheses are reference values for operation with fX = 10 MHz. 2. fX: X1 input clock oscillation frequency User's Manual U15836EJ4V0UD 293 CHAPTER 15 STANDBY FUNCTION (2) Oscillation stabilization time select register (OSTS) This register is used to select the X1 oscillation stabilization wait time when STOP mode is released. The wait time set by OSTS is valid only after STOP mode is released when the X1 input clock is selected as the CPU clock. After STOP mode is released when the Ring-OSC clock is selected, check the oscillation stabilization time using OSTC. OSTS can be set by an 8-bit memory manipulation instruction. RESET input sets OSTS to 05H. Figure 15-2. Format of Oscillation Stabilization Time Select Register (OSTS) Address: FFA4H Symbol OSTS After reset: 05H 7 0 6 0 R/W 5 0 4 0 3 0 2 OSTS2 1 OSTS1 0 OSTS0 OSTS2 0 0 0 1 1 OSTS1 0 1 1 0 0 Other than above OSTS0 1 0 1 0 1 11 Oscillation stabilization time selection 2 /fX (204.8 s) 2 /fX (819.2 s) 13 2 /fX (1.64 ms) 2 /fX (3.27 ms) 2 /fX (6.55 ms) Setting prohibited 16 15 14 Cautions 1. If the STOP mode is entered and then released while the Ring-OSC clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS The X1 oscillation stabilization time counter counts only during the oscillation stabilization time set by OSTS. Therefore, note that only the statuses during the oscillation stabilization time set by OSTS are set to OSTC after STOP mode has been released. 2. The wait time when STOP mode is released does not include the time after STOP mode release until clock oscillation starts ("a" below) regardless of whether STOP mode is released by RESET input or interrupt generation. STOP mode release X1 pin voltage waveform a Remarks 1. Values in parentheses are reference values for operation with fX = 10 MHz. 2. fX: X1 input clock oscillation frequency 294 User's Manual U15836EJ4V0UD CHAPTER 15 STANDBY FUNCTION 15.2 Standby Function Operation 15.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. HALT mode can be set when the CPU clock before the setting was the X1 input clock or Ring-OSC clock. The operating statuses in the HALT mode are shown below. Table 15-2. Operating Statuses in HALT Mode HALT Mode Setting When HALT Instruction Is Executed While CPU Is Operating Using X1 Input Clock Ring-OSC Oscillation Ring-OSC Oscillation Item System clock CPU Port (output latch) 16-bit timer/event counter 00 8-bit timer/event counter 50 8-bit timer H0 Continues Stopped Note 1 When HALT Instruction Is Executed While CPU Is Operating Using Ring-OSC Clock X1 Input Clock Oscillation Continues X1 Input Clock Oscillation Stopped Clock supply to the CPU is stopped Operation stopped Holds the status before HALT mode was set Operable Operable Operable Operation not guaranteed Operation not guaranteed when count clock other than TI50 is selected Operation not guaranteed when count clock other than TM50 output is selected during 8-bit timer/event counter 50 operation Operation not guaranteed when count 7 clock other than fR/2 is selected - Operable 8-bit timer H1 Watchdog timer Ring-OSC cannot be Note 2 stopped Ring-OSC can be Note 2 stopped A/D converter Serial interface UART0 Note 3 Operable Operable Operation stopped Operable Operable Operable Operation not guaranteed Operation not guaranteed when serial clock other than TM50 output is selected during 8-bit timer/event counter 50 operation Operation not guaranteed when serial clock other than external SCK10 is selected Operation stopped Operable Operation stopped UART6 CSI10 Operable Clock monitor Power-on-clear function Note 4 Operable Operable Operable Operable Low-voltage detection function External interrupt Notes 1. 2. 3. 4. When "Stopped by software" is selected for Ring-OSC by a mask option and Ring-OSC is stopped by software (for mask options, see CHAPTER 20 MASK OPTIONS). "Ring-OSC cannot be stopped" or "Ring-OSC can be stopped by software" can be selected by a mask option. PD780102, 780103, and 78F0103 only. When "POC used" is selected by a mask option. User's Manual U15836EJ4V0UD 295 CHAPTER 15 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgement is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgement is disabled, the next address instruction is executed. Figure 15-3. HALT Mode Release by Interrupt Request Generation Interrupt request Wait HALT instruction Standby release signal Operating mode Status of CPU X1 input clock or Ring-OSC clock HALT mode Oscillation Wait Operating mode Remarks 1. The broken lines indicate the case when the interrupt request which has released the standby mode is acknowledged. 2. The wait time is as follows: * When vectored interrupt servicing is carried out: 8 or 9 clocks * When vectored interrupt servicing is not carried out: 2 or 3 clocks 296 User's Manual U15836EJ4V0UD CHAPTER 15 STANDBY FUNCTION (b) Release by RESET input When the RESET signal is input, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 15-4. HALT Mode Release by RESET Input (1) When X1 input clock is used as CPU clock HALT instruction RESET signal Operation Operating mode stopped (17/fR) (Ring-OSC clock) Oscillation Oscillates stopped Reset period Oscillation stabilization time (211/fXP to 216/fXP) Status of CPU Operating mode (X1 input clock) HALT mode Oscillates X1 input clock (2) When Ring-OSC clock is used as CPU clock HALT instruction RESET signal Operation Operating mode stopped (17/fR) (Ring-OSC clock) Oscillation Oscillates stopped Reset period Status of CPU Operating mode (Ring-OSC clock) HALT mode Oscillates Ring-OSC clock Remarks 1. fXP: X1 input clock oscillation frequency 2. fR: Ring-OSC clock oscillation frequency Table 15-3. Operation in Response to Interrupt Request in HALT Mode Release Source Maskable interrupt request 0 0 1 x 1 0 1 x x MKxx 0 PRxx 0 IE 0 ISP x Operation Next address instruction execution Interrupt servicing execution 0 0 0 1 1 1 x - 0 x 1 x x Next address instruction execution Interrupt servicing execution 1 RESET input - HALT mode held Reset processing x: Don't care User's Manual U15836EJ4V0UD 297 CHAPTER 15 STANDBY FUNCTION 15.2.2 STOP mode (1) STOP mode setting and operating statuses The STOP mode is set by executing the STOP instruction. It can be set when the CPU clock before the setting was the X1 input clock or Ring-OSC clock. Caution Because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. Thus, the STOP mode is reset to the HALT mode immediately after execution of the STOP instruction and the system returns to the operating mode as soon as the wait time set using the oscillation stabilization time select register (OSTS) has elapsed. The operating statuses in the STOP mode are shown below. Table 15-4. Operating Statuses in STOP Mode HALT Mode Setting When STOP Instruction Is Executed While CPU Is Operating Using X1 Input Clock Ring-OSC Oscillation Ring-OSC Oscillation Item System clock CPU Port (output latch) 16-bit timer/event counter 00 8-bit timer/event counter 50 8-bit timer H0 8-bit timer H1 Watchdog timer Ring-OSC cannot be Note 3 stopped Ring-OSC can be Note 3 stopped A/D converter Serial interface UART0 Note 4 Note 1 When STOP Instruction Is Executed While CPU Is Operating Using Ring-OSC Clock Continues Stopped Only X1 oscillator oscillation is stopped. Clock supply to the CPU is stopped. Operation stopped Holds the status before STOP mode was set Operation stopped Operable only when TI50 is selected as count clock Operable when TM50 output is selected as count clock during 8-bit timer/event counter 50 operation Operable Operable Operation stopped Operation stopped Operable only when TM50 output is selected as count clock during 8-bit timer/event counter 50 operation Operable only when external SCK10 is selected as serial clock Operation stopped Note 5 Note 2 Operation stopped - Operable Operable Note 2 UART6 CSI10 Clock monitor Power-on-clear function Operable Operable Operable Low-voltage detection function External interrupt Notes 1. When "Stopped by software" is selected for Ring-OSC by a mask option and Ring-OSC is stopped by software (for mask options, see CHAPTER 20 MASK OPTIONS). 2. Operable only when fR/27 is selected as count clock. 3. "Ring-OSC cannot be stopped" or "Ring-OSC can be stopped by software" can be selected by a mask option. 4. PD780102, 780103, and 78F0103 only. 5. When "POC used" is selected by a mask option. 298 User's Manual U15836EJ4V0UD CHAPTER 15 STANDBY FUNCTION (2) STOP mode release Figure 15-5. Operation Timing When STOP Mode Is Released STOP mode release STOP mode X1 input clock Ring-OSC clock X1 input clock is selected as CPU clock when STOP instruction is executed Ring-OSC clock is selected as CPU clock when STOP instruction is executed Operation stopped (17/fR) HALT status (oscillation stabilization time set by OSTS) X1 input clock Ring-OSC clock X1 input clock Clock switched by software User's Manual U15836EJ4V0UD 299 CHAPTER 15 STANDBY FUNCTION The STOP mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is released. out. If interrupt acknowledgment is disabled, the next address instruction is executed. Figure 15-6. STOP Mode Release by Interrupt Request Generation (1) When X1 input clock is used as CPU clock STOP instruction Wait (set by OSTS) After the oscillation stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried Standby release signal Oscillation stabilization wait status Oscillates Oscillation stabilization time (set by OSTS) Status of CPU Operating mode (X1 input clock) Oscillates STOP mode Oscillation stopped Operating mode (X1 input clock) X1 input clock (2) When Ring-OSC clock is used as CPU clock STOP instruction Standby release signal Operation stopped (17/fR) Oscillates Status of CPU Ring-OSC clock Operating mode (Ring-OSC clock) STOP mode Operating mode (Ring-OSC clock) Remarks 1. The broken lines indicate the case when the interrupt request that has released the standby mode is acknowledged. 2. fR: Ring-OSC clock oscillation frequency 300 User's Manual U15836EJ4V0UD CHAPTER 15 STANDBY FUNCTION (b) Release by RESET input When the RESET signal is input, STOP mode is released and a reset operation is performed after the oscillation stabilization time has elapsed. Figure 15-7. STOP Mode Release by RESET Input (1) When X1 input clock is used as CPU clock STOP instruction RESET signal Operation Operating mode stopped (17/fR) (Ring-OSC clock) Oscillation Oscillates stopped Oscillation stabilization time (211/fXP to 216/fXP) Reset period Status of CPU Operating mode (X1 input clock) Oscillates STOP mode Oscillation stopped X1 input clock (2) When Ring-OSC clock is used as CPU clock STOP instruction RESET signal Operation Operating mode stopped (17/fR) (Ring-OSC clock) Oscillation Oscillates stopped Reset period Status of CPU Operating mode (Ring-OSC clock) Ring-OSC clock STOP mode Oscillates Remarks 1. fXP: X1 input clock oscillation frequency 2. fR: Ring-OSC clock oscillation frequency Table 15-5. Operation in Response to Interrupt Request in STOP Mode Release Source Maskable interrupt request 0 0 1 x 1 0 1 x x MKxx 0 PRxx 0 IE 0 ISP x Operation Next address instruction execution Interrupt servicing execution 0 0 0 1 1 1 x - 0 x 1 x x Next address instruction execution Interrupt servicing execution 1 RESET input - STOP mode held Reset processing x: Don't care User's Manual U15836EJ4V0UD 301 CHAPTER 16 RESET FUNCTION The following five operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer program loop detection (3) Internal reset by clock monitor X1 clock oscillation stop detection (4) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit (5) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI) External and internal resets have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H when the reset signal is input. A reset is applied when a low level is input to the RESET pin, the watchdog timer overflows, X1 clock oscillation stop is detected by the clock monitor, or by POC and LVI circuit voltage detection, and each item of hardware is set to the status shown in Table 16-1. Each pin is high impedance during reset input or during the oscillation stabilization time just after reset release, except for P130, which is low-level output. When a high level is input to the RESET pin, the reset is released and program execution starts using the RingOSC clock after the CPU clock operation has stopped for 17/fR (s). A reset generated by the watchdog timer and clock monitor sources is automatically released after the reset, and program execution starts using the Ring-OSC clock after the CPU clock operation has stopped for 17/fR (s) (see Figures 16-2 to 16-4). Reset by POC and LVI circuit power supply detection is automatically released when VDD > VPOC or VDD > VLVI after the reset, and program execution starts using the Ring-OSC clock after the CPU clock operation has stopped for 17/fR (s) (see CHAPTER 18 POWER-ON-CLEAR CIRCUIT and CHAPTER 19 LOW-VOLTAGE DETECTOR). Cautions 1. For an external reset, input a low level for 10 s or more to the RESET pin. 2. During reset input, the X1 input clock and Ring-OSC clock stop oscillating. 3. When the STOP mode is released by a reset, the STOP mode contents are held during reset input. However, the port pins become high-impedance, except for P130, which is set to lowlevel output. 302 User's Manual U15836EJ4V0UD Figure 16-1. Block Diagram of Reset Function Internal bus Reset control flag register (RESF) WDTRF Set Watchdog timer reset signal Clear Clear Clear CLMRF Set LVIRF Set CHAPTER 16 RESET FUNCTION Clock monitor reset signal User's Manual U15836EJ4V0UD Reset signal RESET Power-on-clear circuit reset signal Reset signal to LVIM/LVIS register Low-voltage detector reset signal Reset signal Caution An LVI circuit internal reset does not reset the LVI circuit. Remarks 1. LVIM: Low-voltage detection register 2. LVIS: Low-voltage detection level selection register 303 CHAPTER 16 RESET FUNCTION Figure 16-2. Timing of Reset by RESET Input Ring-OSC clock X1 input clock Reset period (Oscillation stop) Operation stop (17/fR) Normal operation (Reset processing, Ring-OSC clock) CPU clock RESET Normal operation Internal reset signal Delay Port pin Delay Hi-ZNote Note The port pins become high impedance, except for P130, which is set to low-level output. Figure 16-3. Timing of Reset Due to Watchdog Timer Overflow Ring-OSC clock X1 input clock CPU clock Watchdog timer overflow Normal operation Reset period (Oscillation stop) Operation stop (17/fR) Normal operation (Reset processing, Ring-OSC clock) Internal reset signal Port pin Hi-ZNote Note The port pins become high impedance, except for P130, which is set to low-level output. Caution A watchdog timer internal reset resets the watchdog timer. 304 User's Manual U15836EJ4V0UD CHAPTER 16 RESET FUNCTION Figure 16-4. Timing of Reset in STOP Mode by RESET Input Ring-OSC clock X1 input clock STOP instruction execution Operation stop Normal Reset period Stop status operation (Oscillation stop) (Oscillation stop) (17/fR) CPU clock RESET Normal operation (Reset processing, Ring-OSC clock) Internal reset signal Delay Port pin Delay Hi-ZNote Note The port pins become high impedance, except for P130, which is set to low-level output. Remark For the reset timing of the power-on-clear circuit and low-voltage detector, see CHAPTER 18 POWERON-CLEAR CIRCUIT and CHAPTER 19 LOW-VOLTAGE DETECTOR. User's Manual U15836EJ4V0UD 305 CHAPTER 16 RESET FUNCTION Table 16-1. Hardware Statuses After Reset Acknowledgment (1/2) Hardware Program counter (PC) Status After Reset Note 1 Acknowledgment The contents of the reset vector table (0000H, 0001H) are set. Undefined 02H Data memory General-purpose registers Port registers (P0 to P3, P12, P13) (output latches) Port mode registers (PM0, PM1, PM3, PM12) Pull-up resistor option registers (PU0, PU1, PU3, PU12) Input switch control register (ISC) Internal memory size switching register (IMS) Internal expansion RAM size switching register (IXS) Processor clock control register (PCC) Ring-OSC mode register (RCM) Main clock mode register (MCM) Main OSC control register (MOC) Oscillation stabilization time select register (OSTS) Oscillation stabilization time counter status register (OSTC) 16-bit timer/event counter 00 Timer counter 00 (TM00) Capture/compare registers 000, 010 (CR000, CR010) Mode control register 00 (TMC00) Prescaler mode register 00 (PRM00) Capture/compare control register 00 (CRC00) Timer output control register 00 (TOC00) 8-bit timer/event counter 50 Timer counter 50 (TM50) Compare register 50 (CR50) Timer clock selection register 50 (TCL50) Mode control register 50 (TMC50) 8-bit timer/event counters H0, H1 Undefined Undefined Note 2 Stack pointer (SP) Program status word (PSW) RAM Note 2 00H (undefined only for P2) FFH 00H 00H CFH 0CH 00H 00H 00H 00H 05H 00H 0000H 0000H 00H 00H 00H 00H 00H 00H 00H 00H Compare registers 00, 10, 01, 11 (CMP00, CMP10, CMP01, CMP11) 00H Mode registers (TMHMD0, TMHMD1) 00H 67H 9AH Undefined 00H 00H 00H 00H Watchdog timer Mode register (WDTM) Enable register (WDTE) A/D converter Conversion result register (ADCR) Mode register (ADM) Analog input channel specification register (ADS) Power-fail comparison mode register (PFM) Power-fail comparison threshold register (PFT) Notes 1. 2. During reset input or oscillation stabilization time wait, only the PC contents among the hardware statuses become undefined. All other hardware statuses remain unchanged after reset. When a reset is executed in the standby mode, the pre-reset status is held even after reset. User's Manual U15836EJ4V0UD 306 CHAPTER 16 RESET FUNCTION Table 16-1. Hardware Statuses After Reset Acknowledgment (2/2) Hardware Serial interface UART0 Note 1 Status After Reset Acknowledgment FFH FFH 01H 1FH FFH FFH 01H 00H 00H 00H FFH 16H Undefined 00H 00H 00H 00H 00H 00H Note 2 Receive buffer register 0 (RXB0) Transmit shift register 0 (TXS0) Asynchronous serial interface operation mode register 0 (ASIM0) Baud rate generator control register 0 (BRGC0) Serial interface UART6 Receive buffer register 6 (RXB6) Transmit buffer register 6 (TXB6) Asynchronous serial interface operation mode register 6 (ASIM6) Asynchronous serial interface reception error status register 6 (ASIS6) Asynchronous serial interface transmission error status register 6 (ASIF6) Clock selection register 6 (CKSR6) Baud rate generator control register 6 (BRGC6) Asynchronous serial interface control register 6 (ASICL6) Serial interface CSI10 Transmit buffer register 10 (SOTB10) Serial I/O shift register 10 (SIO10) Serial operation mode register 10 (CSIM10) Serial clock selection register 10 (CSIC10) Clock monitor Reset function Low-voltage detector Mode register (CLM) Reset control flag register (RESF) Low-voltage detection register (LVIM) Low-voltage detection level selection register (LVIS) Note 2 00H 00H Note 2 Interrupt Request flag registers 0L, 0H, 1L (IF0L, IF0H, IF1L) Mask flag registers 0L, 0H, 1L (MK0L, MK0H, MK1L) Priority specification flag registers 0L, 0H, 1L (PR0L, PR0H, PR1L) External interrupt rising edge enable register (EGP) External interrupt falling edge enable register (EGN) FFH FFH 00H 00H Notes 1. 2. PD780102, 780103, and 78F0103 only. These values vary depending on the reset source. Reset Source RESET Input Reset by POC Reset by WDT Reset by CLM Reset by LVI Register RESF LVIM LVIS See Table 16-2. Cleared (00H) Cleared (00H) Cleared (00H) Cleared (00H) Held User's Manual U15836EJ4V0UD 307 CHAPTER 16 RESET FUNCTION 16.1 Register for Confirming Reset Source Many internal reset generation sources exist in the 78K0/KB1. The reset control flag register (RESF) is used to store which source has generated the reset request. RESF can be read by an 8-bit memory manipulation instruction. RESET input, reset input by power-on-clear (POC) circuit, and reading RESF clear RESF to 00H. Figure 16-5. Format of Reset Control Flag Register (RESF) Address: FFACH Symbol RESF After reset: 00H 7 0 6 0 Note R 5 0 4 WDTRF 3 0 2 0 1 CLMRF 0 LVIRF WDTRF 0 1 Internal reset request by watchdog timer (WDT) Internal reset request is not generated, or RESF is cleared. Internal reset request is generated. CLMRF 0 1 Internal reset request by clock monitor (CLM) Internal reset request is not generated, or RESF is cleared. Internal reset request is generated. LVIRF 0 1 Internal reset request by low-voltage detector (LVI) Internal reset request is not generated, or RESF is cleared. Internal reset request is generated. Note The value after reset varies depending on the reset source. Caution Do not read data via a 1-bit memory manipulation instruction. The status of RESF when a reset request is generated is shown in Table 16-2. Table 16-2. RESF Status When Reset Request Is Generated Reset Source Flag WDTRF CLMRF LVIRF Cleared (0) Cleared (0) Set (1) Held Held Held Set (1) Held Held Held Set (1) RESET input Reset by POC Reset by WDT Reset by CLM Reset by LVI 308 User's Manual U15836EJ4V0UD CHAPTER 17 CLOCK MONITOR 17.1 Functions of Clock Monitor The clock monitor samples the X1 input clock using the on-chip Ring-OSC, and generates an internal reset signal when the X1 input clock is stopped. When a reset signal is generated by the clock monitor, bit 1 (CLMRF) of the reset control flag register (RESF) is set to 1. For details of RESF, see CHAPTER 16 RESET FUNCTION. The clock monitor automatically stops under the following conditions. * Reset is released and during the oscillation stabilization time * In STOP mode and during the oscillation stabilization time * When the X1 input clock is stopped by software (MSTOP = 1 or MCC = 1) and during the oscillation stabilization time * When the Ring-OSC clock is stopped Remark MSTOP: Bit 7 of the main OSC control register (MOC) 17.2 Configuration of Clock Monitor The clock monitor includes the following hardware. Table 17-1. Configuration of Clock Monitor Item Control register Clock monitor mode register (CLM) Configuration Figure 17-1. Block Diagram of Clock Monitor Internal bus Clock monitor mode register (CLM) CLME X1 oscillation control signal (MSTOP) X1 oscillation stabilization status (OSTC overflow) Operation mode controller X1 input clock Ring-OSC clock X1 oscillation monitor circuit Internal reset signal Remark MSTOP: Bit 7 of the main OSC control register (MOC) OSTC: Oscillation stabilization time counter status register (OSTC) User's Manual U15836EJ4V0UD 309 CHAPTER 17 CLOCK MONITOR 17.3 Register Controlling Clock Monitor The clock monitor is controlled by the clock monitor mode register (CLM). (1) Clock monitor mode register (CLM) This register sets the operation mode of the clock monitor. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 17-2. Format of Clock Monitor Mode Register (CLM) Address: FFA9H Symbol CLM 7 0 After reset: 00H 6 0 R/W 5 0 4 0 3 0 2 0 1 0 <0> CLME CLME 0 1 Enables/disables clock monitor operation Disables clock monitor operation Enables clock monitor operation Cautions 1. Once bit 0 (CLME) is set to 1, it cannot be cleared to 0 except by RESET input or the internal reset signal. 2. If the reset signal is generated by the clock monitor, CLME is cleared to 0 and bit 1 (CLMRF) of the reset control flag register (RESF) is set to 1. 310 User's Manual U15836EJ4V0UD CHAPTER 17 CLOCK MONITOR 17.4 Operation of Clock Monitor This section explains the functions of the clock monitor. The monitor start and stop conditions are as follows. CPU Operation Clock X1 input clock Operation Mode STOP mode X1 Input Clock Status Stopped Ring-OSC Clock Status Oscillating Stopped RESET input Note Clock Monitor Status Stopped Oscillating Stopped Note Normal operation mode HALT mode Ring-OSC clock STOP mode RESET input Normal operation mode HALT mode Oscillating Oscillating Stopped Note Operating Stopped Stopped Stopped Oscillating Oscillating Stopped Operating Stopped Note The Ring-OSC clock is stopped only when the "Ring-OSC can be stopped by software" is selected by a mask option. If "Ring-OSC cannot be stopped" is selected, the Ring-OSC clock cannot be stopped. The clock monitor timing is as shown in Figure 17-3. User's Manual U15836EJ4V0UD 311 CHAPTER 17 CLOCK MONITOR Figure 17-3. Timing of Clock Monitor (1/4) (1) When internal reset is executed by oscillation stop of X1 input clock 4 clocks of Ring-OSC clock X1 input clock Ring-OSC clock Internal reset signal CLME CLMRF (2) Clock monitor status after RESET input (CLME = 1 is set after RESET input and during X1 input clock oscillation stabilization time) Normal operation Clock supply stopped CPU operation X1 input clock Reset Normal operation (Ring-OSC clock) Oscillation stopped Ring-OSC clock Oscillation stopped RESET 17 clocks Oscillation stabilization time Set to 1 by software CLME Clock monitor status Monitoring Monitoring stopped Monitoring Waiting for end of oscillation stabilization time RESET input clears bit 0 (CLME) of the clock monitor mode register (CLM) to 0 and stops the clock monitor operation. Even if CLME is set to 1 by software during the oscillation stabilization time (reset value of OSTS register is 05H (216/fXP)) of the X1 input clock, monitoring is not performed until the oscillation stabilization time of the X1 input clock ends. Monitoring is automatically started at the end of the oscillation stabilization time. 312 User's Manual U15836EJ4V0UD CHAPTER 17 CLOCK MONITOR Figure 17-3. Timing of Clock Monitor (2/4) (3) Clock monitor status after RESET input (CLME = 1 is set after RESET input and at the end of X1 input clock oscillation stabilization time) Normal operation Clock supply stopped CPU operation X1 input clock Reset Normal operation (Ring-OSC clock) Oscillation stabilization time Ring-OSC clock 17 clocks RESET Set to 1 by software CLME Clock monitor status Monitoring Monitoring stopped Monitoring RESET input clears bit 0 (CLME) of the clock monitor mode register (CLM) to 0 and stops the clock monitor operation. When CLME is set to 1 by software at the end of the oscillation stabilization time (reset value of OSTS register is 05H (216/fXP)) of the X1 input clock, monitoring is started. (4) Clock monitor status after STOP mode is released (CLME = 1 is set when CPU clock operates on X1 input clock and before entering STOP mode) Normal operation CPU operation X1 input clock (CPU clock) STOP Oscillation stabilization time Normal operation Oscillation stopped Ring-OSC clock Oscillation stabilization time (time set by OSTS register) CLME Clock monitor status Monitoring Monitoring stopped Monitoring When bit 0 (CLME) of the clock monitor mode register (CLM) is set to 1 before entering STOP mode, monitoring automatically starts at the end of the X1 input clock oscillation stabilization time. Monitoring is stopped in STOP mode and during the oscillation stabilization time. User's Manual U15836EJ4V0UD 313 CHAPTER 17 CLOCK MONITOR Figure 17-3. Timing of Clock Monitor (3/4) (5) Clock monitor status after STOP mode is released (CLME = 1 is set when CPU clock operates on Ring-OSC clock and before entering STOP mode) Normal operation Clock supply stopped CPU operation X1 input clock STOP Normal operation Oscillation stopped Ring-OSC clock (CPU clock) Oscillation stabilization time (time set by OSTS register) 17 clocks CLME Clock monitor status Monitoring Monitoring stopped Monitoring stopped Monitoring When bit 0 (CLME) of the clock monitor mode register (CLM) is set to 1 before entering STOP mode, monitoring automatically starts at the end of the X1 input clock oscillation stabilization time. Monitoring is stopped in STOP mode and during the oscillation stabilization time. (6) Clock monitor status after X1 input clock oscillation is stopped by software CPU operation X1 input clock Oscillation stopped Ring-OSC clock Oscillation stabilization time (time set by OSTS register) Normal operation (Ring-OSC clock or subsystem clockNote) MSTOP CLME Clock monitor status Monitoring Monitoring stopped Monitoring stopped Monitoring When bit 0 (CLME) of the clock monitor mode register (CLM) is set to 1 before or while oscillation of the X1 input clock is stopped, monitoring automatically starts at the end of the X1 input clock oscillation stabilization time. Monitoring is stopped when oscillation of the X1 input clock is stopped and during the oscillation stabilization time. 314 User's Manual U15836EJ4V0UD CHAPTER 17 CLOCK MONITOR Figure 17-3. Timing of Clock Monitor (4/4) (7) Clock monitor status after Ring-OSC clock oscillation is stopped by software CPU operation X1 input clock Normal operation (X1 input clock or subsystem clock) Ring-OSC clock Oscillation stopped RSTOP Note CLME Clock monitor status Monitoring Monitoring stopped Monitoring When bit 0 (CLME) of the clock monitor mode register (CLM) is set to 1 before or while oscillation of the Ring-OSC clock is stopped, monitoring automatically starts after the Ring-OSC clock is stopped. Monitoring is stopped when oscillation of the Ring-OSC clock is stopped. Note If it is specified by a mask option that Ring-OSC cannot be stopped, the setting of bit 0 (RSTOP) of the Ring-OSC mode register (RCM) is invalid. To set RSTOP, be sure to confirm that bit 1 (MCS) of the main clock mode register (MCM) is 1. User's Manual U15836EJ4V0UD 315 CHAPTER 18 POWER-ON-CLEAR CIRCUIT 18.1 Functions of Power-on-Clear Circuit The power-on-clear circuit (POC) has the following functions. * Generates internal reset signal at power on. * Compares supply voltage (VDD) and detection voltage (VPOC), and generates internal reset signal when VDD < VPOC. * The following can be selected by a mask option. * * * POC disabled POC used (detection voltage: VPOC = 2.85 V 0.15 V)Note POC used (detection voltage: VPOC = 3.5 V 0.2 V) Note This option cannot be selected in (A1) and (A2) grade products because the supply voltage VDD is 3.3 to 5.5 V. Caution If an internal reset signal is generated in the POC circuit, the reset control flag register (RESF) is cleared to 00H. Remark This product incorporates multiple hardware functions that generate an internal reset signal. A flag that indicates the reset cause is located in the reset control flag register (RESF) for when an internal reset signal is generated by the watchdog timer (WDT), low-voltage-detection (LVI) circuit, or clock monitor. RESF is not cleared to 00H and the flag is set to 1 when an internal reset signal is generated by WDT, LVI, or the clock monitor. For details of the RESF, see CHAPTER 16 RESET FUNCTION. 316 User's Manual U15836EJ4V0UD CHAPTER 18 POWER-ON-CLEAR CIRCUIT 18.2 Configuration of Power-on-Clear Circuit A block diagram of the power-on-clear circuit is shown in Figure 18-1. Figure 18-1. Block Diagram of Power-on-Clear Circuit VDD VDD Mask option + - Internal reset signal Detection voltage source (VPOC) Note Selected by mask option. 18.3 Operation of Power-on-Clear Circuit In the power-on-clear circuit, the supply voltage (VDD) and detection voltage (VPOC) are compared, and when VDD < VPOC, an internal reset signal is generated. Figure 18-2. Timing of Internal Reset Signal Generation in Power-on-Clear Circuit Supply voltage (VDD) POC detection voltage (VPOC) 2.7 V Time Internal reset signal User's Manual U15836EJ4V0UD 317 CHAPTER 18 POWER-ON-CLEAR CIRCUIT 18.4 Cautions for Power-on-Clear Circuit In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the POC detection voltage (VPOC), the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action. ; The Ring-OSC clock is set as the CPU clock when the reset signal is generated Reset Checking cause of resetNote 2 Power-on-clear ; The cause of reset (power-on-clear, WDT, LVI, or clock monitor) can be identified by the RESF register. Start timer (set to 50 ms) ; 8-bit timer H1 can operate with the Ring-OSC clock. Source: fR (480 kHz (MAX.))/27 x compare value 200 = 53 ms (fR: Ring-OSC clock oscillation frequency) Note 1 Check stabilization of oscillation ; Check the stabilization of oscillation of the X1 input clock by using the OSTC register. Change CPU clock ; Change the CPU clock from the Ring-OSC clock to the X1 input clock. No 50 ms has passed? (TMIFH1 = 1?) ; TMIFH1 = 1: Interrupt request is generated. Yes Initialization processing ; Initialization of ports Notes 1. 2. If reset is generated again during this period, initialization processing is not started. A flowchart is shown on the next page. 318 User's Manual U15836EJ4V0UD CHAPTER 18 POWER-ON-CLEAR CIRCUIT Figure 18-3. Example of Software Processing After Release of Reset (2/2) * Checking reset cause Check reset cause WDTRF of RESF register = 1? Yes No Reset processing by watchdog timer CLMRF of RESF register = 1? Yes No Reset processing by clock monitor LVIRF of RESF register = 1? Yes No Reset processing by low-voltage detector Power-on-clear/external reset generated User's Manual U15836EJ4V0UD 319 CHAPTER 19 LOW-VOLTAGE DETECTOR 19.1 Functions of Low-Voltage Detector The low-voltage detector (LVI) has following functions. * Compares supply voltage (VDD) and detection voltage (VLVI), and generates an internal interrupt signal or internal reset signal when VDD < VLVI. * Detection levels (seven levels)Note of supply voltage can be changed by software. * Interrupt or reset function can be selected by software. * Operable in STOP mode. Note Five levels in the case of (A1) grade products and (A2) grade products. When the low-voltage detector is used to reset, bit 0 (LVIRF) of the reset control flag register (RESF) is set to 1 if reset occurs. For details of RESF, see CHAPTER 16 RESET FUNCTION. 19.2 Configuration of Low-Voltage Detector A block diagram of the low-voltage detector is shown below. Figure 19-1. Block Diagram of Low-Voltage Detector VDD Low-voltage detection level selector VDD N-ch Selector Internal reset signal + - INTLVI Detection voltage source (VLVI) 3 LVIS2 LVIS1 LVIS0 Low-voltage detection level selection register (LVIS) Internal bus LVION LVIE LVIMD LVIF Low-voltage detection register (LVIM) 320 User's Manual U15836EJ4V0UD CHAPTER 19 LOW-VOLTAGE DETECTOR 19.3 Registers Controlling Low-Voltage Detector The low-voltage detector is controlled by the following registers. * Low-voltage detection register (LVIM) * Low-voltage detection level selection register (LVIS) (1) Low-voltage detection register (LVIM) This register sets low-voltage detection and the operation mode. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears LVIM to 00H. Figure 19-2. Format of Low-Voltage Detection Register (LVIM) Address: FFBEH Symbol LVIM <7> LVION After reset: 00H 6 0 R/WNote 1 5 0 <4> LVIE 3 0 2 0 <1> LVIMD <0> LVIF LVION 0 1 Notes 2, 3 Enables low-voltage detection operation Disables operation Enables operation LVIE Notes 2, 4, 5 Specifies reference voltage generator Disables operation Enables operation 0 1 LVIMD 0 1 Note 2 Low-voltage detection operation mode selection Generates interrupt signal when supply voltage (VDD) < detection voltage (VLVI) Generates internal reset signal when supply voltage (VDD) < detection voltage (VLVI) LVIF 0 1 Note 6 Low-voltage detection flag Supply voltage (VDD) > detection voltage (VLVI), or when operation is disabled Supply voltage (VDD) < detection voltage (VLVI) Notes 1. 2. 3. Bit 0 is read-only. LVION, LVIE, and LVIMD are cleared to 0 in the case of a reset other than an LVI reset. These are not cleared to 0 in the case of an LVI reset. When LVION is set to 1, operation of the comparator in the LVI circuit is started. confirmed at LVIF. Use software to instigate a wait of at least 0.2 ms from when LVION is set to 1 until the voltage is 4. 5. 6. If "POC cannot be used" is selected by a mask option, wait for 2 ms or more by software from when LVIE is set to 1 until LVION is set to 1. If "POC used" is selected by a mask option, setting of LVIE is invalid because the reference voltage generator in the LVI circuit always operates. The value of LVIF is output as the interrupt request signal INTLVI when LVION = 1 and LVIMD = 0. User's Manual U15836EJ4V0UD 321 CHAPTER 19 LOW-VOLTAGE DETECTOR Caution To stop LVI, follow either of the procedures below. * When using 8-bit manipulation instruction: Write 00H to LVIM. * When using 1-bit memory manipulation instruction: Clear LVION to 0 first and then clear LVIE to 0. (2) Low-voltage detection level selection register (LVIS) This register selects the low-voltage detection level. This register can be set by an 8-bit memory manipulation instruction. RESET input clears LVIS to 00H. Figure 19-3. Format of Low-Voltage Detection Level Selection Register (LVIS) Address: FFBFH Symbol LVIS 7 0 After reset: 00H 6 0 R/W 5 0 4 0 3 0 2 LVIS2 1 LVIS1 0 LVIS0 LVIS2 0 0 0 0 1 1 1 1 LVIS1 0 0 1 1 0 0 1 1 LVIS0 0 1 0 1 0 1 0 1 VLVI0 (4.3 V 0.2 V) VLVI1 (4.1 V 0.2 V) VLVI2 (3.9 V 0.2 V) VLVI3 (3.7 V 0.2 V) VLVI4 (3.5 V 0.2 V) Note 1 Detection level VLVI5 (3.3 V 0.15 V) VLVI6 (3.1 V 0.15 V) Setting prohibited Notes 1, 2 Notes 1, 2 Notes 1. When the detection voltage of the POC circuit is specified as VPOC = 3.5 V 0.2 V by a mask option, do not select VLVI4 to VLVI6 as the LVI detection voltage. Even if VLVI4 to VLVI6 are selected, the POC circuit has priority. 2. This setting is prohibited in (A1) grade products and (A2) grade products. Caution Be sure to clear bits 3 to 7 to 0. 322 User's Manual U15836EJ4V0UD CHAPTER 19 LOW-VOLTAGE DETECTOR 19.4 Operation of Low-Voltage Detector The low-voltage detector can be used in the following two modes. * Used as reset Compares the supply voltage (VDD) and detection voltage (VLVI), and generates an internal reset signal when VDD < VLVI. * Used as interrupt Compares the supply voltage (VDD) and detection voltage (VLVI), and generates an interrupt signal (INTLVI) when VDD < VLVI. The operation is set as follows. (1) When used as reset * When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set the detection voltage using bits 2 to 0 (LVIS2 to LVIS0) of the low-voltage detection level selection register (LVIS). <3> Set bit 4 (LVIE) of the low-voltage detection register (LVIM) to 1 (enables reference voltage generator operation). <4> Use software to instigate a wait of at least 2 ms. <5> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation). <6> Use software to instigate a wait of at least 0.2 ms. <7> Wait until it is checked that (supply voltage (VDD) > detection voltage (VLVI)) by bit 0 (LVIF) of LVIM. <8> Set bit 1 (LVIMD) of LVIM to 1 (generates internal reset signal when supply voltage (VDD) < detection voltage (VLVI)). Figure 19-4 shows the timing of the internal reset signal generated by the low-voltage detector. The numbers in this timing chart correspond to <1> to <8> above. Cautions 1. <1> must always be executed. When LVIMK = 0, an interrupt may occur immediately after the processing in <5>. 2. If "POC used" is selected by a mask option, procedures <3> and <4> are not required. 3. If supply voltage (VDD) > detection voltage (VLVI) when LVIM is set to 1, an internal reset signal is not generated. * When stopping operation Either of the following procedures must be executed. * When using 8-bit memory manipulation instruction: Write 00H to LVIM. When using 1-bit memory manipulation instruction: Clear LVIMD to 0, LVION to 0, and LVIE to 0 in that order. * User's Manual U15836EJ4V0UD 323 CHAPTER 19 LOW-VOLTAGE DETECTOR Figure 19-4. Timing of Low-Voltage Detector Internal Reset Signal Generation Supply voltage (VDD) LVI detection voltage (VLVI) POC detection voltage (VPOC) 2.7 V <2> LVIMK flag (set by software) <1>Note 1 Time LVIE flag (set by software) Not cleared <3> <4> 2 ms or longer Not cleared Clear Not cleared Clear LVION flag (set by software) <5> Not cleared <6> 0.2 ms or longer LVIF flag <7> LVIMD flag (set by software) Note 2 Clear Not cleared Not cleared Clear <8> LVIRF flagNote 3 LVI reset signal Cleared by software POC reset signal Cleared by software Internal reset signal Notes 1. 2. 3. The LVIMK flag is set to "1" by RESET input. The LVIF flag may be set (1). LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, see CHAPTER 16 RESET FUNCTION. Remark <1> to <8> in Figure 19-4 above correspond to <1> to <8> in the description of "when starting operation" in 19.4 (1) When used as reset. 324 User's Manual U15836EJ4V0UD CHAPTER 19 LOW-VOLTAGE DETECTOR (2) When used as interrupt * When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set the detection voltage using bits 2 to 0 (LVIS2 to LVIS0) of the low-voltage detection level selection register (LVIS). <3> Set bit 4 (LVIE) of the low-voltage detection register (LVIM) to 1 (enables reference voltage generator operation). <4> Use software to instigate a wait of at least 2 ms. <5> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation). <6> Use software to instigate a wait of at least 0.2 ms. <7> Wait until it is checked that (supply voltage (VDD) > detection voltage (VLVI)) by bit 0 (LVIF) of LVIM. <8> Clear the interrupt request flag of LVI (LVIIF) to 0. <9> Release the interrupt mask flag of LVI (LVIMK). <10> Execute the EI instruction (when vector interrupts are used). Figure 19-5 shows the timing of the interrupt signal generated by the low-voltage detector. The numbers in this timing chart correspond to <1> to <9> above. Caution If "POC used" is selected by a mask option, procedures <3> and <4> are not required. * When stopping operation Either of the following procedures must be executed. * When using 8-bit memory manipulation instruction: Write 00H to LVIM. When using 1-bit memory manipulation instruction: Clear LVION to 0 first, and then clear LVIE to 0. * User's Manual U15836EJ4V0UD 325 CHAPTER 19 LOW-VOLTAGE DETECTOR Figure 19-5. Timing of Low-Voltage Detector Interrupt Signal Generation Supply voltage (VDD) LVI detection voltage (VLVI) POC detection voltage (VPOC) 2.7 V <2> LVIMK flag (set by software) <1>Note 1 <9> Cleared by software LVIE flag (set by software) Time <3> <4> 2 ms or longer LVION flag (set by software) <5> <6> 0.2 ms or longer LVIF flag <7> Note 2 INTLVI LVIIF flag Note 2 <8> Cleared by software Internal reset signal Notes 1. 2. Remark The LVIMK flag is set to "1" by RESET input. The LVIF and LVIIF flags may be set (1). <1> to <9> in Figure 19-5 above correspond to <1> to <9> in the description of "when starting operation" in 19.4 (2) When used as interrupt. 326 User's Manual U15836EJ4V0UD CHAPTER 19 LOW-VOLTAGE DETECTOR 19.5 Cautions for Low-Voltage Detector In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the LVI detection voltage (VLVI), the operation is as follows depending on how the low-voltage detector is used. (1) When used as reset The system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking action (1) below. (2) When used as interrupt Interrupt requests may be frequently generated. Take action (2) below. In this system, take the following actions. User's Manual U15836EJ4V0UD 327 CHAPTER 19 LOW-VOLTAGE DETECTOR Figure 19-6. Example of Software Processing After Release of Reset (1/2) * If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage ; The Ring-OSC clock is set as the CPU clock when the reset signal is generated Reset Checking cause of resetNote 2 LVI ; The cause of reset (power-on-clear, WDT, LVI, or clock monitor) can be identified by the RESF register. Start timer (set to 50 ms) ; 8-bit timer H1 can operate with the Ring-OSC clock. Source: fR (480 kHz (MAX.))/27 x compare value 200 = 53 ms (fR: Ring-OSC clock oscillation frequency) Note 1 Check stabilization of oscillation ; Check the stabilization of oscillation of the X1 input clock by using the OSTC register. Change CPU clock ; Change the CPU clock from the Ring-OSC clock to the X1 input clock. No 50 ms has passed? (TMIFH1 = 1?) ; TMIFH1 = 1: Interrupt request is generated. Yes Initialization processing ; Initialization of ports Notes 1. 2. If reset is generated again during this period, initialization processing is not started. A flowchart is shown on the next page. 328 User's Manual U15836EJ4V0UD CHAPTER 19 LOW-VOLTAGE DETECTOR Figure 19-6. Example of Software Processing After Release of Reset (2/2) * Checking reset cause Check reset cause WDTRF of RESF register = 1? Yes No Reset processing by watchdog timer CLMRF of RESF register = 1? Yes No Reset processing by clock monitor LVIRF of RESF register = 1? No Yes Power-on-clear/external reset generated Reset processing by low-voltage detector (2) When used as interrupt Check that "supply voltage (VDD) > detection voltage (VLVI)" in the servicing routine of the LVI interrupt by using bit 0 (LVIF) of the low-voltage detection register (LVIM). Clear bit 0 (LVIIF) of interrupt request flag register 0L (IF0L) to 0 and enable interrupts (EI). In a system where the supply voltage fluctuation period is long in the vicinity of the LVI detection voltage, wait for the supply voltage fluctuation period, check that "supply voltage (VDD) > detection voltage (VLVI)" using the LVIF flag, and then enable interrupts (EI). User's Manual U15836EJ4V0UD 329 CHAPTER 20 MASK OPTIONS Mask ROM versions are provided with the following mask options. 1. Power-on-clear (POC) circuit * POC cannot be used * POC used (detection voltage: VPOC = 2.85 V 0.15 V)Note * POC used (detection voltage: VPOC = 3.5 V 0.2 V) 2. Ring-OSC * Cannot be stopped * Can be stopped by software Note This option cannot be selected in (A1) and (A2) grade products because the supply voltage VDD is 3.3 to 5.5 V. Flash memory versions that support the mask options of the mask ROM versions are as follows. Table 20-1. Flash Memory Versions Supporting Mask Options of Mask ROM Versions Mask Option POC Circuit POC cannot be used Ring-OSC Cannot be stopped Can be stopped by software POC used (VPOC = 2.85 V 0.15 V) POC used (VPOC = 3.5 V 0.2 V) Cannot be stopped Can be stopped by software Cannot be stopped Can be stopped by software Flash Memory Version PD78F0103M1, 78F0103M1(A), 78F0103M1(A1) PD78F0103M2, 78F0103M2(A), 78F0103M2(A1) PD78F0103M3, 78F0103M3(A) PD78F0103M4, 78F0103M4(A) PD78F0103M5, 78F0103M5(A), 78F0103M5(A1) PD78F0103M6, 78F0103M6(A), 78F0103M6(A1) 330 User's Manual U15836EJ4V0UD CHAPTER 21 PD78F0103 The PD78F0103 is provided as the flash memory version of the 78K0/KB1. The PD78F0103 replaces the internal mask ROM of the PD780103 with flash memory to which a program can be written, erased, and overwritten while mounted on the board. Table 21-1 lists the differences between the PD78F0103 and the mask ROM versions. Table 21-1. Differences Between PD78F0103 and Mask ROM Versions Item Internal ROM configuration Internal ROM capacity PD78F0103 Flash memory 24 KB Note Mask ROM Versions Mask ROM PD780101: 8 KB PD780102: 16 KB PD780103: 24 KB Note Internal high-speed RAM capacity 768 bytes PD780101: 512 bytes PD780102: 768 bytes PD780103: 768 bytes Available None IC pin VPP pin Electrical specifications, recommended soldering conditions None Available Refer to the description of electrical specifications and recommended soldering conditions. Note The same capacity as the mask ROM versions can be specified by means of the internal memory size switching register (IMS). Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions. When pre-producing an application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask ROM versions. User's Manual U15836EJ4V0UD 331 CHAPTER 21 PD78F0103 21.1 Internal Memory Size Switching Register The PD78F0103 allows users to select the internal memory capacity using the internal memory size switching register (IMS) so that the same memory map as that of the mask ROM versions with a different internal memory capacity can be achieved. IMS is set by an 8-bit memory manipulation instruction. RESET input sets IMS to CFH. Caution The initial value of IMS is "setting prohibited (CFH)". Be sure to set the value of the relevant mask ROM version at initialization. Figure 21-1. Format of Internal Memory Size Switching Register (IMS) Address: FFF0H Symbol IMS After reset: CFH 7 RAM2 6 RAM1 R/W 5 RAM0 4 0 3 ROM3 2 ROM2 1 ROM1 0 ROM0 RAM2 0 0 RAM1 0 1 Other than above RAM0 0 0 768 bytes 512 bytes Internal high-speed RAM capacity selection Setting prohibited ROM3 0 0 0 ROM2 0 1 1 ROM1 1 0 1 ROM0 0 0 0 8 KB 16 KB 24 KB Internal ROM capacity selection Other than above Setting prohibited The IMS settings required to obtain the same memory map as mask ROM versions are shown in Table 21-2. Table 21-2. Internal Memory Size Switching Register Settings Target Mask ROM Versions IMS Setting 42H 04H 06H PD780101 PD780102 PD780103 Caution When using a mask ROM version, be sure to set IMS to the value indicated in Table 21-2. 332 User's Manual U15836EJ4V0UD CHAPTER 21 PD78F0103 21.2 Writing with Flash Programmer Data can be written to the flash memory on-board or off-board, by using a dedicated flash programmer. (1) On-board programming The contents of the flash memory can be rewritten after the PD78F0103 has been mounted on the target system. The connectors that connect the dedicated flash programmer must be mounted on the target system. (2) Off-board programming Data can be written to the flash memory with a dedicated program adapter (FA series) before the PD78F0103 is mounted on the target system. Remark The FA series is a product of Naito Densei Machida Mfg. Co., Ltd. Table 21-3. Wiring Between PD78F0103 and Dedicated Flash Programmer (1/2) (1) 3-wire serial I/O (CSI10) Pin Configuration of Dedicated Flash Programmer Signal Name SI/RxD SO/TxD SCK CLK I/O Input Output Output Output Pin Function Receive signal Transmit signal Transfer clock Clock to PD78F0103 With CSI10 Pin Name SO10/P12 SI10/RxD0/P11 SCK10/TxD0/P10 X1 X2 /RESET VPP H/S VDD Output Output Input I/O Reset signal Write voltage Handshake signal VDD voltage generation/voltage monitor GND - Ground Note 2 Note 1 With CSI10+HS Pin No. 17 16 15 8 9 10 5 Pin Name SO10/P12 SI10/RxD0/P11 SCK10/TxD0/P10 X1 X2 Note 1 Pin No. 17 16 15 8 9 10 5 20 7 28 6 29 RESET VPP Not needed VDD AVREF VSS AVSS RESET VPP HS/P15/TOH0 VDD AVREF VSS AVSS Not needed 7 28 6 29 Notes 1. 2. When using the clock out of the flash programmer, connect CLK of the programmer to X1, and connect its inverse signal to X2. Flashpro III only User's Manual U15836EJ4V0UD 333 CHAPTER 21 PD78F0103 Table 21-3. Wiring Between PD78F0103 and Dedicated Flash Programmer (2/2) (2) UART (UART0, UART6) Pin Configuration of Dedicated Flash Programmer Signal Name SI/RxD I/O Input Pin Function Receive signal With UART0 Pin Name TxD0/ SCK10/P10 SO/TxD Output Transmit signal RxD0/SI10/ P10 SCK Output Transfer clock Clock to PD78F0103 Not needed Not needed CLK Output X1 X2 /RESET VPP H/S Output Output Input Reset signal Write voltage Handshake signal Note 1 With UART0+HS Pin Name TxD0/ SCK10/P10 Pin No. 15 With UART6 Pin Name TxD6/P13 Pin No. 18 Pin No. 15 16 RxD0/SI10/ P11 Not needed 16 RxD6/P14 19 Not needed Not needed Not needed 8 9 10 5 Not needed X1 X2 Note 1 8 9 10 5 X1 X2 Note 1 8 9 10 5 Not needed RESET VPP Not needed RESET VPP RESET VPP Not needed HS/P15/TOH0 20 VDD I/O VDD voltage generation/voltage VDD monitor Note 2 7 28 6 29 VDD AVREF VSS AVSS 7 28 6 29 VDD AVREF VSS AVSS 7 28 6 29 AVREF VSS AVSS GND - Ground Notes 1. 2. When using the clock out of the flash programmer, connect CLK of the programmer to X1, and connect its inverse signal to X2. Flashpro III only 334 User's Manual U15836EJ4V0UD CHAPTER 21 PD78F0103 Examples of the recommended connection when using the adapter for flash memory writing are shown below. Figure 21-2. Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O (CSI10) Mode VDD (2.7 to 5.5 V)Note GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 GND VDD LVDD 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FRASH WRITER INTERFACE SI SO SCK CLK /RESET VPP RESERVE/HS Note PD78F0103, 78F0103(A): 2.7 to 5.5 V PD78F0103(A1): 3.3 to 5.5 V User's Manual U15836EJ4V0UD 335 CHAPTER 21 PD78F0103 Figure 21-3. Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O (CSI10 + HS) Mode VDD (2.7 to 5.5 V)Note GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 GND VDD LVDD 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FRASH WRITER INTERFACE SI SO SCK CLK /RESET VPP RESERVE/HS Note PD78F0103, 78F0103(A): 2.7 to 5.5 V PD78F0103(A1): 3.3 to 5.5 V 336 User's Manual U15836EJ4V0UD CHAPTER 21 PD78F0103 Figure 21-4. Example of Wiring Adapter for Flash Memory Writing in UART (UART0) Mode VDD (2.7 to 5.5 V)Note GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 GND VDD LVDD 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FRASH WRITER INTERFACE SI SO SCK CLK /RESET VPP RESERVE/HS Note PD78F0103, 78F0103(A): 2.7 to 5.5 V PD78F0103(A1): 3.3 to 5.5 V User's Manual U15836EJ4V0UD 337 CHAPTER 21 PD78F0103 Figure 21-5. Example of Wiring Adapter for Flash Memory Writing in UART (UART0 + HS) Mode VDD (2.7 to 5.5 V)Note GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 GND VDD LVDD 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FRASH WRITER INTERFACE SI SO SCK CLK /RESET VPP RESERVE/HS Note PD78F0103, 78F0103(A): 2.7 to 5.5 V PD78F0103(A1): 3.3 to 5.5 V 338 User's Manual U15836EJ4V0UD CHAPTER 21 PD78F0103 Figure 21-6. Example of Wiring Adapter for Flash Memory Writing in UART (UART6) Mode VDD (2.7 to 5.5 V)Note GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 GND VDD LVDD 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FRASH WRITER INTERFACE SI SO SCK CLK /RESET VPP RESERVE/HS Note PD78F0103, 78F0103(A): 2.7 to 5.5 V PD78F0103(A1): 3.3 to 5.5 V User's Manual U15836EJ4V0UD 339 CHAPTER 21 PD78F0103 21.3 Programming Environment The environment required for writing a program to the flash memory of the PD78F0103 is illustrated below. Figure 21-7. Environment for Writing Program to Flash Memory VPP XXXX YYYY Bxxxxx Cxxxxxx XXXX XXXXXX RS-232C Axxxx VDD PG-FP4 (Flash Pro4) XXXXX XXX YYY STATVE VSS RESET PD78F0103 USBNote Dedicated flash programmer Host machine CSI10/UART0/UART6 Note Flashpro IV only A host machine that controls the dedicated flash programmer is necessary. To interface between the dedicated flash programmer and the PD78F0103, CSI10, UART0, or UART6 is used for manipulation such as writing and erasing. To write the flash memory off-board, a dedicated program adapter (FA series) is necessary. 21.4 Communication Mode Communication between the dedicated flash programmer and the PD78F0103 is established by serial communication via CSI10, UART0, or UART6 of the PD78F0103. (1) CSI10 Transfer rate: 200 kHz to 2 MHz Figure 21-8. Communication with Dedicated Flash Programmer (CSI10) VPP VDD GND XXXX YYYY VPP VDD/AVREF VSS/AVSS RESET SO10 SI10 SCK10 X1 X2 Bxxxxx Cxxxxxx XXXXXX Axxxx XXX YYY PG-FP4 (Flash Pro4) XXXXX STATVE /RESET SI/RxD XXXX Dedicated flash programmer SO/TxD SCK CLK PD78F0103 340 User's Manual U15836EJ4V0UD CHAPTER 21 PD78F0103 (2) CSI communication mode supporting handshake Transfer rate: 200 kHz to 2 MHz Figure 21-9. Communication with Dedicated Flash Programmer (CSI10 + HS) VPP VDD GND XXXX YYYY VPP VDD/AVREF VSS/AVSS RESET SO10 SI10 SCK10 X1 X2 HS Bxxxxx Cxxxxxx XXXXXX Axxxx XXX YYY PG-FP4 (Flash Pro4) XXXXX STATVE /RESET SI/RxD XXXX Dedicated flash programmer SO/TxD SCK CLK H/S PD78F0103 (3) UART0 Transfer rate: 4800 to 38400 bps Figure 21-10. Communication with Dedicated Flash Programmer (UART0) VPP VDD XXXX YYYY VPP VDD/AVREF VSS/AVSS RESET RxD0 TxD0 X1 X2 Bxxxxx Cxxxxxx XXX YYY PG-FP4 (Flash Pro4) XXXXX STATVE XXXX XXXXXX Axxxx GND /RESET SO/TxD SI/RxD CLK Dedicated flash programmer PD78F0103 User's Manual U15836EJ4V0UD 341 CHAPTER 21 PD78F0103 (4) UART communication mode supporting handshake Transfer rate: 4800 to 38400 bps Figure 21-11. Communication with Dedicated Flash Programmer (UART0 + HS) VPP VDD XXXX YYYY VPP VDD/AVREF VSS/AVSS RESET TxD0 RxD0 X1 X2 HS Bxxxxx Cxxxxxx XXXX XXXXXX Axxxx GND PG-FP4 (Flash Pro4) XXXXX XXX YYY STATVE /RESET SI/RxD Dedicated flash programmer SO/TxD CLK H/S PD78F0103 (5) UART6 Transfer rate: 4800 to 76800 bps Figure 21-12. Communication with Dedicated Flash Programmer (UART6) VPP VDD GND XXXX YYYY VPP VDD/AVREF VSS/AVSS RESET TxD6 RxD6 X1 X2 Bxxxxx Cxxxxxx XXXXXX Axxxx XXX YYY PG-FP4 (Flash Pro4) XXXXX STATVE /RESET SI/RxD XXXX Dedicated flash programmer SO/TxD CLK PD78F0103 342 User's Manual U15836EJ4V0UD CHAPTER 21 PD78F0103 If Flashpro III/Flashpro IV is used as the dedicated flash programmer, Flashpro III/Flashpro IV generates the following signal for the PD78F0103. For details, refer to the Flashpro III/Flashpro IV Manual. Table 21-4. Pin Connection Flashpro III/Flashpro IV Signal Name VPP VDD GND CLK /RESET SI/RxD SO/TxD SCK H/S I/O Output I/O - Output Output Input Output Output Input Write voltage VDD voltage generation/voltage monitor Ground Clock output to PD78F0103 Reset signal Receive signal Transmit signal Transfer clock Handshake signal Note 1 PD78F0103 Pin Name VPP VDD, AVREF VSS, AVSS X1, X2 Note 2 Connection CSI00 UART0 UART6 Pin Function RESET SO10/TxD0/TxD6 SI10/RxD0/RxD6 SCK10 HS x x x Notes 1. Frashpro III only 2. For off-board writing only: connect the clock output of the flash programmer to X1 and its inverse signal to X2. Remark : Be sure to connect the pin. : The pin does not have to be connected if the signal is generated on the target board. x: The pin does not have to be connected. : In handshake mode User's Manual U15836EJ4V0UD 343 CHAPTER 21 PD78F0103 21.5 Handling of Pins on Board To write the flash memory on-board, connectors that connect the dedicated flash programmer must be provided on the target system. First provide a function that selects the normal operation mode or flash memory programming mode on the board. When the flash memory programming mode is set, all the pins not used for programming the flash memory are in the same status as immediately after reset. Therefore, if the external device does not recognize the state immediately after reset, the pins must be handled as described below. 21.5.1 VPP pin In the normal operation mode, connect the VPP pin to VSS. In addition, a write voltage of 10.0 V (TYP.) is supplied to the VPP pin in the flash memory programming mode. Perform the following pin handling. (1) Connect pull-down resistor RVPP = 10 k to the VPP pin. (2) Switch the input of the VPP pin to the programmer side by using a jumper on the board or to GND directly. Figure 21-13. Example of Connection of VPP Pin PD78F0103 Dedicated flash programmer connection pin VPP Pull-down resistor (RVPP) 21.5.2 Serial interface pins The pins used by each serial interface are listed below. Table 21-5. Pins Used by Each Serial Interface Serial Interface CSI10 CSI10 + HS UART0 UART0 + HS UART6 Pins Used SO10, SI10, SCK10 SO10, SI10, SCK10, HS/P15 TxD0, RxD0 TxD0, RxD0, HS/P15 TxD6, RxD6 To connect the dedicated flash programmer to the pins of a serial interface that is connected to another device on the board, care must be exercised so that signals do not collide or that the other device does not malfunction. 344 User's Manual U15836EJ4V0UD CHAPTER 21 PD78F0103 (1) Signal collision If the dedicated flash programmer (output) is connected to a pin (input) of a serial interface connected to another device (output), signal collision takes place. To avoid this collision, either isolate the connection with the other device, or make the other device go into an output high-impedance state. Figure 21-14. Signal Collision (Input Pin of Serial Interface) PD78F0103 Signal collision Input pin Dedicated flash programmer connection pin Other device Output pin In the flash memory programming mode, the signal output by the device collides with the signal sent from the dedicated flash programmer. Therefore, isolate the signal of the other device. (2) Malfunction of other device If the dedicated flash programmer (output or input) is connected to a pin (input or output) of a serial interface connected to another device (input), a signal may be output to the other device, causing the device to malfunction. To avoid this malfunction, either isolate the connection with the other device. Figure 21-15. Malfunction of Other Device PD78F0103 Dedicated flash programmer connection pin Other device Input pin Pin If the signal output by the PD78F0103 in the flash memory programming mode affects the other device, isolate the signal of the other device. PD78F0103 Dedicated flash programmer connection pin Other device Input pin Pin If the signal output by the dedicated flash programmer in the flash memory programming mode affects the other device, isolate the signal of the other device. User's Manual U15836EJ4V0UD 345 CHAPTER 21 PD78F0103 21.5.3 RESET pin If the reset signal of the dedicated flash programmer is connected to the RESET pin that is connected to the reset signal generator on the board, signal collision takes place. To prevent this collision, isolate the connection with the reset signal generator. If the reset signal is input from the user system while the flash memory programming mode is set, the flash memory will not be correctly programmed. Do not input any signal other than the reset signal of the dedicated flash programmer. Figure 21-16. Signal Collision (RESET Pin) PD78F0103 Signal collision RESET Dedicated flash programmer connection signal Reset signal generator Output pin In the flash memory programming mode, the signal output by the reset signal generator collides with the signal output by the dedicated flash programmer. Therefore, isolate the signal of the reset signal generator. 21.5.4 Port pins When the flash memory programming mode is set, all the pins not used for flash memory programming enter the same status as that immediately after reset. If external devices connected to the ports do not recognize the port status immediately after reset, the port pin must be connected to VDD or VSS via a resistor. 21.5.5 Other signal pins Connect X1 and X2 in the same status as in the normal operation mode when using the on-board clock. To input the operating clock from the programmer, however, connect the clock out of the programmer to X1, and its inverse signal to X2. 21.5.6 Power supply To use the supply voltage output of the flash programmer, connect the VDD pin to VDD of the flash programmer, and the VSS pin to VSS of the flash programmer. To use the on-board supply voltage, connect in compliance with the normal operation mode. Supply the same other power supplies (AVREF and AVSS) as those in the normal operation mode. Caution VDD In the dedicated flash programmer PG-FP3 or FL-PR3, VDD has a power monitor function. Be sure to connect VDD and VSS to VDD and GND of the dedicated flash programmer. 346 User's Manual U15836EJ4V0UD CHAPTER 21 PD78F0103 21.6 Programming Method 21.6.1 Controlling flash memory The following figure illustrates the procedure to manipulate the flash memory. Figure 21-17. Flash Memory Manipulation Procedure Start VPP pulse supply Flash memory programming mode is set Selecting communication mode Manipulate flash memory End? Yes End No 21.6.2 Flash memory programming mode To rewrite the contents of the flash memory by using the dedicated flash programmer, set the PD78F0103 in the flash memory programming mode. To set the mode, set the VPP pin and clear the reset signal. Change the mode by using a jumper when writing the flash memory on-board. Figure 21-18. Flash Memory Programming Mode VPP pulse 10.0 V VPP VDD VSS RESET Flash memory programming mode 1 2 *** n VPP VSS 10.0 V Normal operation mode Operation mode Flash memory programming mode User's Manual U15836EJ4V0UD 347 CHAPTER 21 PD78F0103 21.6.3 Selecting communication mode In the PD78F0103 a communication mode is selected by inputting pulses (up to 11 pulses) to the VPP pin after the dedicated flash memory programming mode is entered. These VPP pulses are generated by the flash programmer. The following table shows the relationship between the number of pulses and communication modes. Table 21-6. Communication Modes Communication Mode Port (COMM PORT) 3-wire serial I/O (CSI10) 3-wire serial I/O with handshake supported (CSI10 + HS) UART (UART0) UART (UART6) UART with handshake supported (UART0 + HS) SIO-ch0 (SIO ch-0) SIO-H/S (SIO ch-3 + handshake) UART-ch0 (UART ch-0) UART-ch1 (UART ch-1) UART-ch3 (UART ch-3) 4800 to 38400 bpsNotes 2, 3 TxD0, RxD0, HS/P15 11 4800 to 76800 bpsNotes 2, 3 TxD6, RxD6 9 4800 to 38400 bps Notes 2, 3 Standard (TYPE) SettingNote 1 Speed (SIO CLOCK) 200 kHz to 2 MHzNote 2 200 kHz to 2 MHzNote 2 On Target (CPU CLOCK) Arbitrary Frequency (Flashpro Clock) 2 to 10 MHz Multiply Rate (Multiple Rate) 1.0 Pins Used Number of VPP Pulses SO10, SI10, SCK10 SO10, SI10, SCK10, HS/P15 TxD0, RxD0 0 3 8 Notes 1. Selection items for Standard settings on Flashpro IV (TYPE settings on Flashpro III). 2. The possible setting range differs depending on the voltage. For details, refer to the chapters of electrical specifications. 3. Because factors other than the baud rate error, such as the signal waveform slew, also affect UART communication, thoroughly evaluate the slew as well as the baud rate error. Caution When UART0 or UART6 is selected, the receive clock is calculated based on the reset command sent from the dedicated flash programmer after the VPP pulse has been received. Remark Items enclosed in parentheses in the setting item column are the set value and set item when they differ from those of Flashpro IV. 348 User's Manual U15836EJ4V0UD CHAPTER 21 PD78F0103 21.6.4 Communication commands The PD78F0103 communicates with the dedicated flash programmer by using commands. The signals sent from the flash programmer to the PD78F0103 are called commands, and the commands sent from the PD78F0103 to the dedicated flash programmer are called response commands. Figure 21-19. Communication Commands Command XXXX YYYY Bxxxxx Cxxxxxx XXX YYY PG-FP4 (Flash Pro4) XXXXX STATVE XXXX XXXXXX Axxxx Dedicated flash programmer Response command PD78F0103 The flash memory control commands of the PD78F0103 are listed in the table below. All these commands are issued from the programmer and the PD78F0103 performs processing corresponding to the respective commands. Table 21-7. Flash Memory Control Commands Classification Verify Command Name Batch verify command Function Compares the contents of the entire memory with the input data. Erase Blank check Data write Batch erase command Batch blank check command High-speed write command Erases the contents of the entire memory. Checks the erasure status of the entire memory. Writes data by specifying the write address and number of bytes to be written, and executes a verify check. Successive write command Writes data from the address following that of the high-speed write command executed immediately before, and executes a verify check. System setting, control Status read command Oscillation frequency setting command Erase time setting command Write time setting command Baud rate setting command Silicon signature command Reset command Obtains the operation status Sets the oscillation frequency Sets the erase time for batch erase Sets the write time for writing data Sets the baud rate when UART is used Reads the silicon signature information Escapes from each status The PD78F0103 return a response command for the command issued by the dedicated flash programmer. The response commands sent from the PD78F0103 are listed below. Table 21-8. Response Commands Command Name ACK NAK Function Acknowledges command/data. Acknowledges illegal command/data. User's Manual U15836EJ4V0UD 349 CHAPTER 22 INSTRUCTION SET This chapter lists each instruction set of the 78K0/KB1 in table form. For details of each operation and operation code, refer to the separate document 78K/0 Series Instructions User's Manual (U12326E). 22.1 Conventions Used in Operation List 22.1.1 Operand identifiers and specification methods Operands are written in the "Operand" column of each instruction in accordance with the specification method of the instruction operand identifier (refer to the assembler specifications for details). When there are two or more methods, select one of them. Uppercase letters and the symbols #, !, $ and [ ] are keywords and must be written as they are. Each symbol has the following meaning. * #: Immediate data specification * !: Absolute address specification * $: Relative address specification * [ ]: Indirect address specification In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to write the #, !, $, and [ ] symbols. For operand register identifiers r and rp, either function names (X, A, C, etc.) or absolute names (names in parentheses in the table below, R0, R1, R2, etc.) can be used for specification. Table 22-1. Operand Identifiers and Specification Methods Identifier r rp sfr sfrp saddr saddrp addr16 addr11 addr5 word byte bit RBn Specification Method X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7) AX (RP0), BC (RP1), DE (RP2), HL (RP3) Special function register symbol Note Note Special function register symbol (16-bit manipulatable register even addresses only) FE20H to FF1FH Immediate data or labels FE20H to FF1FH Immediate data or labels (even address only) 0000H to FFFFH Immediate data or labels (Only even addresses for 16-bit data transfer instructions) 0800H to 0FFFH Immediate data or labels 0040H to 007FH Immediate data or labels (even address only) 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label RB0 to RB3 Note Addresses from FFD0H to FFDFH cannot be accessed with these operands. Remark For special function register symbols, see Table 3-5 Special Function Register List. 350 User's Manual U15836EJ4V0UD CHAPTER 22 INSTRUCTION SET 22.1.2 Description of operation column A: X: B: C: D: E: H: L: AX: BC: DE: HL: PC: SP: PSW: CY: AC: Z: RBS: IE: NMIS: ( ): : : : A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer Program status word Carry flag Auxiliary carry flag Zero flag Register bank select flag Interrupt request enable flag Non-maskable interrupt servicing flag Memory contents indicated by address or register contents in parentheses Logical product (AND) Logical sum (OR) Exclusive logical sum (exclusive OR) : Inverted data Signed 8-bit data (displacement value) XH, XL: Higher 8 bits and lower 8 bits of 16-bit register addr16: 16-bit immediate data or label jdisp8: 22.1.3 Description of flag operation column (Blank): Not affected 0: 1: x: R: Cleared to 0 Set to 1 Set/cleared according to the result Previously saved value is restored User's Manual U15836EJ4V0UD 351 CHAPTER 22 INSTRUCTION SET 22.2 Operation List Instruction Group 8-bit data transfer Clocks Note 1 Note 2 Mnemonic MOV Operands r, #byte saddr, #byte sfr, #byte A, r r, A A, saddr saddr, A A, sfr sfr, A A, !addr16 !addr16, A PSW, #byte A, PSW PSW, A A, [DE] [DE], A A, [HL] [HL], A A, [HL + byte] [HL + byte], A A, [HL + B] [HL + B], A A, [HL + C] [HL + C], A Note 3 Bytes 2 3 3 1 1 2 2 2 2 3 3 3 2 2 1 1 1 1 2 2 1 1 1 1 Note 3 Operation r byte (saddr) byte sfr byte Ar rA A (saddr) (saddr) A A sfr sfr A A (addr16) (addr16) A PSW byte A PSW PSW A A (DE) (DE) A A (HL) (HL) A A (HL + byte) (HL + byte) A A (HL + B) (HL + B) A A (HL + C) (HL + C) A Ar A (saddr) A (sfr) x x Flag Z AC CY 4 6 - 2 2 4 4 - - 8 8 - - - 4 4 4 4 8 8 6 6 6 6 2 4 - 8 4 4 8 8 8 - 7 7 - - 5 5 5 5 9+n 9+m 7 5 5 5+n 5+m 5+n 5+m 9+n 9+m 7+n 7+m 7+n 7+m - 6 6 Note 3 x x x x XCH A, r A, saddr A, sfr A, !addr16 A, [DE] A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] 1 2 2 3 1 1 2 2 2 10 + n + m A (addr16) 6 + n + m A (DE) 6 + n + m A (HL) 10 + n + m A (HL + byte) 10 + n + m A (HL + B) 10 + n + m A (HL + C) Notes 1. 2. 3. When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed Except "r = A" Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 3. n is the number of waits when the external memory expansion area is read. 4. m is the number of waits when the external memory expansion area is written. 352 User's Manual U15836EJ4V0UD CHAPTER 22 INSTRUCTION SET Instruction Group 16-bit data transfer Mnemonic MOVW Operands rp, #word saddrp, #word sfrp, #word AX, saddrp saddrp, AX AX, sfrp sfrp, AX AX, rp rp, AX AX, !addr16 !addr16, AX Note 3 Bytes 3 4 4 2 2 2 2 1 1 3 3 Note 3 Clocks Note 1 Note 2 Operation rp word (saddrp) word sfrp word AX (saddrp) (saddrp) AX AX sfrp sfrp AX AX rp rp AX Flag Z AC CY 6 8 - 6 6 - - 4 4 10 10 4 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8 - 10 10 8 8 8 8 - - Note 3 12 + 2n AX (addr16) 12 + 2m (addr16) AX - - 8 - - 5 9+n 5+n 9+n 9+n 9+n - 8 - - 5 9+n 5+n 9+n 9+n 9+n AX rp A, CY A + byte (saddr), CY (saddr) + byte A, CY A + r r, CY r + A A, CY A + (saddr) A, CY A + (addr16) A, CY A + (HL) A, CY A + (HL + byte) A, CY A + (HL + B) A, CY A + (HL + C) A, CY A + byte + CY (saddr), CY (saddr) + byte + CY A, CY A + r + CY r, CY r + A + CY A, CY A + (saddr) + CY A, CY A + (addr16) + CY A, CY A + (HL) + CY A, CY A + (HL + byte) + CY A, CY A + (HL + B) + CY A, CY A + (HL + C) + CY x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x XCHW 8-bit operation ADD AX, rp A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] 1 2 3 Note 4 2 2 2 3 1 2 2 2 2 3 ADDC A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] Note 4 2 2 2 3 1 2 2 2 Notes 1. 2. 3. 4. When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed Only when rp = BC, DE or HL Except "r = A" Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 3. n is the number of waits when the external memory expansion area is read. 4. m is the number of waits when the external memory expansion area is written. User's Manual U15836EJ4V0UD 353 CHAPTER 22 INSTRUCTION SET Instruction Group 8-bit operation Mnemonic SUB Operands A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] Note 3 Bytes 2 3 2 2 2 3 1 2 2 2 2 3 Note 3 Clocks Note 1 Note 2 Operation A, CY A - byte (saddr), CY (saddr) - byte A, CY A - r r, CY r - A A, CY A - (saddr) A, CY A - (addr16) A, CY A - (HL) A, CY A - (HL + byte) A, CY A - (HL + B) A, CY A - (HL + C) A, CY A - byte - CY (saddr), CY (saddr) - byte - CY A, CY A - r - CY r, CY r - A - CY A, CY A - (saddr) - CY A, CY A - (addr16) - CY A, CY A - (HL) - CY A, CY A - (HL + byte) - CY A, CY A - (HL + B) - CY A, CY A - (HL + C) - CY A A byte (saddr) (saddr) byte AAr rrA A A (saddr) A A (addr16) A A (HL) A A (HL + byte) A A (HL + B) A A (HL + C) x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Flag Z AC CY x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8 - 8 - - 5 9+n 5+n 9+n 9+n 9+n - 8 - - 5 9+n 5+n 9+n 9+n 9+n - 8 - - 5 9+n 5+n 9+n 9+n 9+n SUBC A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] 2 2 2 3 1 2 2 2 2 3 AND A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] Note 3 2 2 2 3 1 2 2 2 Notes 1. 2. 3. When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed Except "r = A" Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 3. n is the number of waits when the external memory expansion area is read. 354 User's Manual U15836EJ4V0UD CHAPTER 22 INSTRUCTION SET Instruction Group 8-bit operation Mnemonic OR Operands A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] Note 3 Bytes 2 3 2 2 2 3 1 2 2 2 2 3 Note 3 Clocks Note 1 Note 2 Operation A A byte (saddr) (saddr) byte AAr rrA A A (saddr) A A (addr16) A A (HL) A A (HL + byte) A A (HL + B) A A (HL + C) A A byte (saddr) (saddr) byte AAr rrA A A (saddr) A A (addr16) A A (HL) A A (HL + byte) A A (HL + B) A A (HL + C) A - byte (saddr) - byte A-r r-A A - (saddr) A - (addr16) A - (HL) A - (HL + byte) A - (HL + B) A - (HL + C) x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Flag Z AC CY 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8 - 8 - - 5 9+n 5+n 9+n 9+n 9+n - 8 - - 5 9+n 5+n 9+n 9+n 9+n - 8 - - 5 9+n 5+n 9+n 9+n 9+n XOR A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] 2 2 2 3 1 2 2 2 2 3 CMP A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] Note 3 x x x x x x x x x x x x x x x x x x x x 2 2 2 3 1 2 2 2 Notes 1. 2. 3. When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed Except "r = A" Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 3. n is the number of waits when the external memory expansion area is read. User's Manual U15836EJ4V0UD 355 CHAPTER 22 INSTRUCTION SET Instruction Group 16-bit operation Mnemonic ADDW SUBW CMPW Operands AX, #word AX, #word AX, #word X C r saddr Bytes 3 3 3 2 2 1 2 1 2 1 1 1 1 1 1 2 2 2 2 6 6 6 16 25 2 4 2 4 4 4 2 2 2 2 Clocks Note 1 Note 2 Operation AX, CY AX + word AX, CY AX - word AX - word AX A x X AX (Quotient), C (Remainder) AX / C rr+1 (saddr) (saddr) + 1 rr-1 (saddr) (saddr) - 1 rp rp + 1 rp rp - 1 (CY, A7 A0, Am - 1 Am) x 1 time (CY, A0 A7, Am + 1 Am) x 1 time (CY A0, A7 CY, Am - 1 Am) x 1 time (CY A7, A0 CY, Am + 1 Am) x 1 time (HL)3 - 0 (HL)7 - 4 x x x x x x x Flag Z AC CY x x x x x x - - - - - - 6 - 6 - - - - - - Multiply/ divide Increment/ decrement MULU DIVUW INC x x x x DEC r saddr INCW DECW Rotate ROR ROL RORC ROLC ROR4 ROL4 BCD adjustment Bit manipulate ADJBA ADJBS MOV1 rp rp A, 1 A, 1 A, 1 A, 1 [HL] [HL] x x x x 10 12 + n + m A3 - 0 (HL)3 - 0, (HL)7 - 4 A3 - 0, 10 12 + n + m A3 - 0 (HL)7 - 4, (HL)3 - 0 A3 - 0, (HL)7 - 4 (HL)3 - 0 4 4 6 - 4 - 6 6 - 4 - 6 - - 7 7 - 7 7+n 8 8 - 8 Decimal Adjust Accumulator after Addition Decimal Adjust Accumulator after Subtract CY (saddr.bit) CY sfr.bit CY A.bit CY PSW.bit CY (HL).bit (saddr.bit) CY sfr.bit CY A.bit CY PSW.bit CY x x x x x x x x x x x x x CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit saddr.bit, CY sfr.bit, CY A.bit, CY PSW.bit, CY [HL].bit, CY 3 3 2 3 2 3 3 2 3 2 8 + n + m (HL).bit CY Notes 1. 2. When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 3. n is the number of waits when the external memory expansion area is read. 4. m is the number of waits when the external memory expansion area is written. 356 User's Manual U15836EJ4V0UD CHAPTER 22 INSTRUCTION SET Instruction Group Bit manipulate Mnemonic AND1 Operands CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit Bytes 3 3 2 3 2 3 3 2 3 2 3 3 2 3 2 2 3 2 2 2 2 3 2 2 2 1 1 1 6 - 4 - 6 6 - 4 - 6 6 - 4 - 6 4 - 4 - 6 4 - 4 - 6 2 2 2 Clocks Note 1 Note 2 Operation CY CY (saddr.bit) CY CY sfr.bit CY CY A.bit CY CY PSW.bit CY CY (HL).bit CY CY (saddr.bit) CY CY sfr.bit CY CY A.bit CY CY PSW.bit CY CY (HL).bit CY CY (saddr.bit) CY CY sfr.bit CY CY A.bit CY CY PSW.bit CY CY (HL).bit (saddr.bit) 1 sfr.bit 1 A.bit 1 PSW.bit 1 (saddr.bit) 0 sfr.bit 0 A.bit 0 PSW.bit 0 CY 1 CY 0 CY CY x x Flag Z AC CY x x x x x x x x x x x x x x x 7 7 - 7 7+n 7 7 - 7 7+n 7 7 - 7 7+n 6 8 - 6 OR1 CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit XOR1 CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit SET1 saddr.bit sfr.bit A.bit PSW.bit [HL].bit x x 8 + n + m (HL).bit 1 6 8 - 6 - - - CLR1 saddr.bit sfr.bit A.bit PSW.bit [HL].bit x x 8 + n + m (HL).bit 0 1 0 x SET1 CLR1 NOT1 CY CY CY Notes 1. 2. When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 3. n is the number of waits when the external memory expansion area is read. 4. m is the number of waits when the external memory expansion area is written. User's Manual U15836EJ4V0UD 357 CHAPTER 22 INSTRUCTION SET Instruction Group Call/return Mnemonic CALL CALLF Operands !addr16 !addr11 Bytes 3 2 7 5 Clocks Note 1 Note 2 Operation (SP - 1) (PC + 3)H, (SP - 2) (PC + 3)L, PC addr16, SP SP - 2 (SP - 1) (PC + 2)H, (SP - 2) (PC + 2)L, PC15 - 11 00001, PC10 - 0 addr11, SP SP - 2 Flag Z AC CY - - CALLT [addr5] 1 6 - (SP - 1) (PC + 1)H, (SP - 2) (PC + 1)L, PCH (00000000, addr5 + 1), PCL (00000000, addr5), SP SP - 2 BRK 1 6 - (SP - 1) PSW, (SP - 2) (PC + 1)H, (SP - 3) (PC + 1)L, PCH (003FH), PCL (003EH), SP SP - 3, IE 0 RET RETI RETB Stack manipulate PUSH PSW rp POP PSW rp MOVW SP, #word SP, AX AX, SP Unconditional BR branch !addr16 $addr16 AX Conditional BC branch BNC BZ BNZ $addr16 $addr16 $addr16 $addr16 1 1 1 1 1 1 1 4 2 2 3 2 2 2 2 2 2 6 6 6 2 4 2 4 - - - 6 6 8 6 6 6 6 - - - - - - - 10 8 8 - - - - - - - PCH (SP + 1), PCL (SP), SP SP + 2 PCH (SP + 1), PCL (SP), PSW (SP + 2), SP SP + 3 PCH (SP + 1), PCL (SP), PSW (SP + 2), SP SP + 3 (SP - 1) PSW, SP SP - 1 (SP - 1) rpH, (SP - 2) rpL, SP SP - 2 PSW (SP), SP SP + 1 rpH (SP + 1), rpL (SP), SP SP + 2 SP word SP AX AX SP PC addr16 PC PC + 2 + jdisp8 PCH A, PCL X PC PC + 2 + jdisp8 if CY = 1 PC PC + 2 + jdisp8 if CY = 0 PC PC + 2 + jdisp8 if Z = 1 PC PC + 2 + jdisp8 if Z = 0 RRR RRR RRR Notes 1. 2. When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 358 User's Manual U15836EJ4V0UD CHAPTER 22 INSTRUCTION SET Instruction Group Mnemonic Operands saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16 Bytes 3 4 3 3 3 4 4 3 4 3 4 4 3 4 3 2 2 3 2 1 2 2 2 2 8 - 8 - 10 10 - 8 - 10 10 - 8 - 10 6 6 8 4 2 - - 6 6 Clocks Note 1 Note 2 Operation PC PC + 3 + jdisp8 if (saddr.bit) = 1 PC PC + 4 + jdisp8 if sfr.bit = 1 PC PC + 3 + jdisp8 if A.bit = 1 PC PC + 3 + jdisp8 if PSW.bit = 1 PC PC + 3 + jdisp8 if (HL).bit = 1 PC PC + 4 + jdisp8 if (saddr.bit) = 0 PC PC + 4 + jdisp8 if sfr.bit = 0 PC PC + 3 + jdisp8 if A.bit = 0 PC PC + 4 + jdisp8 if PSW. bit = 0 PC PC + 3 + jdisp8 if (HL).bit = 0 PC PC + 4 + jdisp8 if (saddr.bit) = 1 then reset (saddr.bit) PC PC + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit PC PC + 3 + jdisp8 if A.bit = 1 then reset A.bit PC PC + 4 + jdisp8 if PSW.bit = 1 then reset PSW.bit x Flag Z AC CY Conditional BT branch 9 11 - 9 11 + n 11 11 - 11 11 + n 12 12 - 12 BF saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16 BTCLR saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16 x x 12 + n + m PC PC + 3 + jdisp8 if (HL).bit = 1 then reset (HL).bit - - 10 - - 6 6 - - B B - 1, then PC PC + 2 + jdisp8 if B 0 C C -1, then PC PC + 2 + jdisp8 if C 0 (saddr) (saddr) - 1, then PC PC + 3 + jdisp8 if (saddr) 0 RBS1, 0 n No Operation IE 1 (Enable Interrupt) IE 0 (Disable Interrupt) Set HALT Mode Set STOP Mode DBNZ B, $addr16 C, $addr16 saddr, $addr16 CPU control SEL NOP EI DI HALT STOP RBn Notes 1. 2. When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 3. n is the number of waits when the external memory expansion area is read. 4. m is the number of waits when the external memory expansion area is written. User's Manual U15836EJ4V0UD 359 CHAPTER 22 INSTRUCTION SET 22.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ Second Operand #byte A rNote sfr saddr !addr16 PSW [DE] [HL] [HL + byte] $addr16 [HL + B] First Operand A [HL + C] 1 None ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH MOV XCH ADD SUB AND OR XOR CMP MOV XCH ADD SUB AND OR XOR CMP MOV MOV XCH MOV XCH ADD SUB AND OR XOR CMP MOV XCH ADD SUB AND OR XOR CMP ROR ROL RORC ROLC ADDC ADDC SUBC SUBC ADDC ADDC SUBC SUBC r MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP INC DEC B, C sfr saddr MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP !addr16 PSW MOV MOV MOV MOV MOV DBNZ DBNZ INC DEC PUSH POP [DE] [HL] MOV MOV ROR4 ROL4 [HL + byte] [HL + B] [HL + C] X C MOV MULU DIVUW Note Except r = A 360 User's Manual U15836EJ4V0UD CHAPTER 22 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Second Operand First Operand AX ADDW SUBW CMPW rp MOVW MOVW Note #word AX rp Note sfrp saddrp !addr16 SP None MOVW XCHW MOVW MOVW MOVW MOVW INCW DECW PUSH POP sfrp saddrp !addr16 SP MOVW MOVW MOVW MOVW MOVW MOVW MOVW Note Only when rp = BC, DE, HL (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR Second Operand First Operand A.bit MOV1 BT BF BTCLR sfr.bit MOV1 BT BF BTCLR saddr.bit MOV1 BT BF BTCLR PSW.bit MOV1 BT BF BTCLR [HL].bit MOV1 BT BF BTCLR CY MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 A.bit sfr.bit saddr.bit PSW.bit [HL].bit CY $addr16 None User's Manual U15836EJ4V0UD 361 CHAPTER 22 INSTRUCTION SET (4) Call instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand First Operand Basic instruction BR CALL BR CALLF CALLT BR BC BNC BZ BNZ Compound instruction BT BF BTCLR DBNZ AX !addr16 !addr11 [addr5] $addr16 (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP 362 User's Manual U15836EJ4V0UD CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) Target products: PD780101, 780102, 780103, 78F0103, 780101(A), 780102(A), 780103(A), 78F0103(A) Absolute Maximum Ratings (TA = 25C) Parameter Supply voltage Symbol VDD VSS AVREF AVSS VPP Input voltage VI1 Conditions Ratings -0.3 to +6.5 -0.3 to +0.3 -0.3 to VDD + 0.3 -0.3 to +0.3 Note 1 Unit V V V V V Note 1 PD78F0103, 78F0103(A) only Note 2 P00 to P03, P10 to P17, P20 to P23, P30 to P33, P120, P130, X1, X2, RESET -0.3 to +10.5 -0.3 to VDD + 0.3 -0.3 to +10.5 -0.3 to VDD + 0.3 Note 1 V VI2 VPP in flash programming mode (PD78F0103, 78F0103(A) only) V Output voltage Analog input voltage VO VAN V Note 1 AVSS - 0.3 to AVREF + 0.3 and -0.3 to VDD + 0.3 Per pin Total of pins P30 to P33, P120 P00 to P03, P10 to P17, P130 Total of all pins -50 20 P30 to P33, P120 P00 to P03, P10 to P17, P130 Total of all pins 60 -40 to +85 -10 to +85 -65 to +150 -40 to +125 35 35 -10 -30 -30 V Note 1 Output current, high IOH mA mA mA mA mA mA mA Output current, low IOL Per pin Total of all pins mA C Operating ambient temperature Storage temperature TA In normal operation mode In flash memory programming Tstg PD780101, 780102, 780103, 780101(A), 780102(A), 780103(A) C PD78F0103, 78F0103(A) Note 1. Must be 6.5 V or lower. (Refer to Note 2 on the next page.) Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U15836EJ4V0UD 363 CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) Note 2. Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash memory is written. * When supply voltage rises VPP must exceed VDD 10 s or more after VDD has reached the lower-limit value (2.7 V) of the operating voltage range (see a in the figure below). * When supply voltage drops VDD must be lowered 10 s or more after VPP falls below the lower-limit value (2.7 V) of the operating voltage range of VDD (see b in the figure below). 2.7 V 0V a b VDD VPP 2.7 V 0V 364 User's Manual U15836EJ4V0UD CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) X1 Oscillator Characteristics (TA = -40 to +85C, 2.7 V VDD 5.5 V, 2.7 V AVREF VDD, VSS = AVSS = 0 V) Resonator Ceramic resonator Recommended Circuit Parameter Oscillation frequency (fXP) Note Conditions 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V 2.7 V VDD < 3.3 V MIN. 2.0 2.0 2.0 TYP. MAX. 10 8.38 5.0 Unit MHz VSS X1 X2 C1 C2 Crystal resonator VSS X1 X2 Oscillation frequency (fXP) Note 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V 2.7 V VDD < 3.3 V 2.0 2.0 2.0 10 8.38 5.0 MHz C1 C2 External clock X1 input frequency 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V 2.7 V VDD < 3.3 V 2.0 2.0 2.0 46 56 96 10 8.38 5.0 500 500 500 MHz X1 X2 (fXP) Note X1 input high-/lowlevel width (tXH, tXL) 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V 2.7 V VDD < 3.3 V ns Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Caution When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. Ring-OSC Oscillator Characteristics (TA = -40 to +85C, 2.7 V VDD 5.5 V, 2.7 V AVREF VDD, VSS = AVSS = 0 V) Resonator On-chip Ring-OSC oscillator Parameter Oscillation frequency (fR) Conditions MIN. 120 TYP. 240 MAX. 480 Unit kHz User's Manual U15836EJ4V0UD 365 CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) Recommended Oscillator Constants Caution For the resonator selection of the PD780101(A), 780102(A), and 780103(A) and oscillator constants, users are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. (a) PD780101, 780102, 780103 X1 oscillation: Ceramic resonator (TA = -40 to +85C) Manufacturer Part Number SMD/Lead Frequency (MHz) Recommended Circuit Constants C1 (pF) Murata Mfg. CSTCC2M00G56 CSTCR4M00G55 CSTCR4M00G55U CSTCR4M00G56 CSTCR4M00G56U CSTCR4M19G55 CSTCR4M19G55U CSTLS4M19G56 CSTLS4M19G56U CSTCR4M91G55 CSTCR4M91G55U CSTCS4M91G56 CSTCS4M91G56U CSTCR5M00G55 CSTCR5M00G55U CSTLS5M00G56 CSTLS5M00G56U CSTCR6M00G55 CSTCR6M00G55U CSTLS6M00G56 CSTLS6M00G56U CSTCE8M00G52 CSTLS8M00G53 CSTLS8M00G53U CSTCE10M0G52 CSTLS10M0G53 CSTLS10M0G53U SMD Lead 10.0 SMD Lead 8.00 Lead SMD 6.00 Lead SMD 5.00 Lead SMD 4.915 Lead SMD 4.194 Lead SMD SMD 2.00 4.00 C2 (pF) Oscillation Voltage Range MIN. (V) 2.7 MAX. (V) 5.5 Internal Internal (47) (47) Internal Internal (39) (39) Internal Internal (47) (47) Internal Internal (39) (39) Internal Internal (47) (47) Internal Internal (39) (39) Internal Internal (47) (47) Internal Internal (39) (39) Internal Internal (47) (47) Internal Internal (39) (39) Internal Internal (47) (47) Internal Internal (10) (10) Internal Internal (15) (15) Internal Internal (10) (10) Internal Internal (15) (15) Caution The oscillator constants shown above are reference values based on evaluation in a specific environment by the resonator manufacturer. If it is necessary to optimize the oscillator characteristics in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use the 78K0/KB1 so that the internal operation conditions are within the specifications of the DC and AC characteristics. 366 User's Manual U15836EJ4V0UD CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (b) PD78F0103 X1 oscillation: Ceramic resonator (TA = -40 to +85C) Manufacturer Part Number SMD/Lead Frequency (MHz) Recommended Circuit Constants C1 (pF) Murata Mfg. CSTCSS2M00G56 CSTCC2M45G56 SMD SMD 2.00 2.457 C2 (pF) Oscillation Voltage Range MIN. (V) 2.7 MAX. (V) 5.5 Internal Internal (47) (47) Internal Internal (47) (47) Internal Internal (15) (15) Internal Internal (15) (15) CSTCR4M00G53 CSTCR4M00G53093 CSTLS4M00G53 CSTLS4M00G53093 CSTCR5M00G53 CSTCR5M00G53093 CSTLS5M00G53 CSTLS5M00G53093 CSTCR6M00G53 CSTCR6M00G53U CSTLS6M00G53 CSTLS6M00G53U CSTCE8M38G52 SMD 4.00 Lead SMD 5.00 Internal Internal (15) (15) Internal Internal (15) (15) Lead SMD 6.00 Internal Internal (15) (15) Internal Internal (15) (15) Lead SMD 8.388 Internal Internal (10) (10) Internal Internal (15) (15) CSTLS8M38G53 CSTLS8M38G53093 CSTCE10M0G52 CSTLS10M0G53 CSTLS10M0G53093 Lead SMD Lead 10.0 Internal Internal (10) (10) Internal Internal (15) (15) Caution The oscillator constants shown above are reference values based on evaluation in a specific environment by the resonator manufacturer. If it is necessary to optimize the oscillator characteristics in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use the 78K0/KB1 so that the internal operation conditions are within the specifications of the DC and AC characteristics. User's Manual U15836EJ4V0UD 367 CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (c) PD78F0103(A) X1 oscillation: Ceramic resonator (TA = -40 to +85C) Manufacturer Part Number SMD/Lead Frequency (MHz) Recommended Circuit Constants C1 (pF) Murata Mfg. CSTCC2M00G56A CSTCC2M45G56A SMD 2.00 2.457 C2 (pF) Oscillation Voltage Range MIN. (V) 2.7 MAX. (V) 5.5 Internal Internal (47) (47) Internal Internal (47) (47) Internal Internal (15) (15) Internal Internal (15) (15) Internal Internal (15) (15) Internal Internal (10) (10) Internal Internal (10) (10) CSTCR4M00G53A 4.00 CSTCR5M00G53A 5.00 CSTCR6M00G53A 6.00 CSTCE8M38G52A 8.388 CSTCE10M0G52A 10.0 Caution The oscillator constants shown above are reference values based on evaluation in a specific environment by the resonator manufacturer. If it is necessary to optimize the oscillator characteristics in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use the 78K0/KB1 so that the internal operation conditions are within the specifications of the DC and AC characteristics. 368 User's Manual U15836EJ4V0UD CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) DC Characteristics (TA = -40 to +85C, 2.7 V VDD 5.5 V, 2.7 V AVREF VDD, VSS = AVSS = 0 V) (1/3) Parameter Output current, high Symbol IOH Per pin Total of P30 to P33, P120 Conditions 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V Output current, low IOL Per pin Total of P30 to P33, P120 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V Input voltage, high VIH1 VIH2 VIH3 VIH4 Input voltage, low VIL1 VIL2 VIL3 VIL4 Output voltage, high VOH P12, P13, P15 0.7VDD MIN. TYP. MAX. -5 -25 -25 -40 -10 10 30 30 50 10 VDD VDD AVREF VDD 0.3VDD 0.2VDD 0.3AVREF 0.4 Unit mA mA mA mA mA mA mA mA mA mA V V V V V V V V V V V 1.3 1.3 0.4 3 3 20 -3 -20 3 -3 10 0 30 100 0.2VDD V V V Total of P00 to P03, P10 to P17, P130 4.0 V VDD 5.5 V Total of all pins Total of P00 to P03, P10 to P17, P130 4.0 V VDD 5.5 V Total of all pins P00 to P03, P10, P11, P14, P16, P17, P30 to P33, P120, 0.8VDD RESET P20 to P23 X1, X2 P12, P13, P15 P00 to P03, P10, P11, P14, P16, P17, P30 to P33, P120, RESET P20 to P23 X1, X2 Total of P30 to P33, P120 pins IOH = -25 mA Total of P00 to P03, P10 to P17, P130 pins IOH = -25 mA IOH = -100 A 4.0 V VDD 5.5 V, IOH = -5 mA 4.0 V VDD 5.5 V, IOH = -5 mA 2.7 V VDD < 4.0 V 4.0 V VDD 5.5 V, IOL = 10 mA 4.0 V VDD 5.5 V, IOL = 10 mA 2.7 V VDD < 4.0 V P00 to P03, P10 to P17, P30 to P33, P120, RESET P20 to P23 X1, X2 Note 2 Note 1 Note 1 0.7AVREF VDD - 0.5 0 0 0 0 VDD - 1.0 VDD - 1.0 VDD - 0.5 Output voltage, low VOL Total of P30 to P33, P120 pins IOL = 30 mA Total of P00 to P03, P10 to P17, P130 pins IOL = 30 mA IOL = 400 A Input leakage current, high ILIH1 VI = VDD VI = AVREF A A A A A A A k V ILIH2 Input leakage current, low ILIL1 ILIL2 Output leakage current, high ILOH Output leakage current, low Pull-up resistance value VPP supply voltage (PD78F0103, 78F0103(A) only) ILOL R VPP1 VI = VDD VI = 0 V P00 to P03, P10 to P17, P20 to P23, P30 to P33, P120, RESET X1, X2 Note 2 VO = VDD VO = 0 V VI = 0 V In normal operation mode Notes 1. When used as a digital input port, set AVREF = VDD. 2. When the inverse level of X1 is input to X2. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U15836EJ4V0UD 369 CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) DC Characteristics (2/3): PD78F0103, 78F0103(A) (TA = -40 to +85C, 2.7 V VDD 5.5 V, 2.7 V AVREF VDD, VSS = AVSS = 0 V) Parameter Supply current Note 1 Symbol IDD1 X1 crystal oscillation operating mode IDD2 Note 2 Conditions fXP = 10 MHz, VDD = 5.0 V 10% fXP = 5 MHz, VDD = 3.0 V 10% fXP = 10 MHz, VDD = 5.0 V 10% fXP = 5 MHz, VDD = 3.0 V 10% Note 3 Note 3 MIN. TYP. MAX. Unit 11.6 Note 4 When A/D converter is stopped When A/D converter is operating When A/D converter is stopped When A/D converter is operating Note 4 19.5 21.5 6.4 7.6 2.8 5.5 mA mA mA mA mA mA mA mA mA mA 12.6 4 4.6 1.4 X1 crystal oscillation HALT mode When peripheral functions are stopped When peripheral functions are operating When peripheral functions are stopped When peripheral functions are operating 0.32 0.64 1.9 IDD3 Ring-OSC operating mode Note 5 VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 5.0 V 10% POC: OFF, RING: OFF POC: OFF, RING: ON POC: ON Note 6 0.37 0.29 0.1 14 3.5 17.5 0.05 7.5 3.5 11 1.51 1.16 30 58 35.5 63.5 10 25 15.5 30.5 IDD4 STOP mode A A A A A A A A , RING: OFF , RING: ON POC: ON VDD = 3.0 V 10% Note 6 POC: OFF, RING: OFF POC: OFF, RING: ON POC: ON Note 6 , RING: OFF , RING: ON POC: ON Note 6 Notes 1. 2. 3. 4. 5. 6. Total current flowing through the internal power supply (VDD). Peripheral operation current is included (however, the current that flows through the pull-up resistors of ports is not included). IDD1 includes peripheral operation current. When PCC = 00H. Total current flowing through VDD and AVREF pins. When X1 oscillator is stopped. Including when LVIE (bit 4 of LVIM) = 1 in the PD78F0103M1, 78F0103M2, 78F0103M1(A), and 78F0103M2(A). 370 User's Manual U15836EJ4V0UD CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) DC Characteristics (3/3): PD780101, 780102, 780103, 780101(A), 780102(A), 780103(A) (TA = -40 to +85C, 2.7 V VDD 5.5 V, 2.7 V AVREF VDD, VSS = AVSS = 0 V) Parameter Supply current Note 1 Symbol IDD1 X1 crystal fXP = 10 MHz, oscillation VDD = 5.0 V 10% operating mode IDD2 Note 2 Conditions When A/D converter is stopped Note 3 MIN. TYP. MAX. Unit 6 Note 4 10.9 12.9 3.1 4.3 2.6 4.8 mA mA mA mA mA mA mA mA mA mA When A/D converter is operating When A/D converter is stopped 7 1.7 fXP = 5 MHz, VDD = 3.0 V 10% Note 3 When A/D converter is operating Note 4 2.3 1.3 X1 crystal fXP = 10 MHz, oscillation VDD = 5.0 V 10% HALT mode fXP = 5 MHz, VDD = 3.0 V 10% When peripheral functions are stopped When peripheral functions are operating When peripheral functions are stopped When peripheral functions are operating 0.25 0.5 1.1 IDD3 Ring-OSC VDD = 5.0 V 10% operating mode Note 5 0.18 0.11 POC: OFF, RING: OFF POC: OFF, RING: ON POC: ON Note 6 0.72 0.44 30 58 35.5 63.5 10 25 15.5 30.5 VDD = 3.0 V 10% VDD = 5.0 V 10% IDD4 STOP mode 0.1 14 3.5 17.5 0.05 7.5 3.5 11 A A A A A A A A , RING: OFF , RING: ON POC: ON VDD = 3.0 V 10% Note 6 POC: OFF, RING: OFF POC: OFF, RING: ON POC: ON Note 6 , RING: OFF , RING: ON POC: ON Note 6 Notes 1. 2. 3. 4. 5. 6. Total current flowing through the internal power supply (VDD). Peripheral operation current is included (however, the current that flows through the pull-up resistors of ports is not included). IDD1 includes peripheral operation current. When PCC = 00H. Total current flowing through VDD and AVREF pins. When X1 oscillator is stopped. Including when LVIE (bit 4 of LVIM) = 1 with POC-OFF selected by a mask option. User's Manual U15836EJ4V0UD 371 CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) AC Characteristics (1) Basic operation (TA = -40 to +85C, 2.7 V VDD 5.5 V, 2.7 V AVREF VDD, VSS = AVSS = 0 V) Parameter Instruction cycle (minimum instruction execution time) Symbol TCY X1 input clock Conditions 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V 2.7 V VDD < 3.3 V Ring-OSC clock TI000, TI010 input high-level width, low-level width tTIH0, tTIL0 2.7 V VDD < 4.0 V TI50 input frequency fTI5 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V TI50 input high-level width, low- tTIH5, level width Interrupt input high-level width, low-level width RESET low-level width tTIL5 tINTH, tINTL tRSL 10 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 50 100 1 4.0 V VDD 5.5 V MIN. 0.2 0.238 0.4 4.17 2/fsam+ 0.1 Note TYP. MAX. 16 16 16 Unit s s s s s s 8.33 16.67 2/fsam+ 0.2 Note 10 5 MHz ns ns s s Note Selection of fsam = fXP, fXP/4, fXP/256 is possible using bits 0 and 1 (PRM000, PRM001) of prescaler mode register 00 (PRM00). Note that when selecting the TI000 valid edge as the count clock, fsam = fXP. TCY vs. VDD (X1 Input Clock Operation) 20.0 16.0 Cycle time TCY [ s] 10.0 5.0 Guaranteed operation range 2.0 1.0 0.4 0.238 0.2 0.1 0 1.0 2.0 3.0 2.7 3.3 4.0 5.0 5.5 6.0 Supply voltage VDD [V] 372 User's Manual U15836EJ4V0UD CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (2) Serial interface (TA = -40 to +85C, 2.7 V VDD 5.5 V, 2.7 V AVREF VDD, VSS = AVSS = 0 V) (a) UART mode (UART6, dedicated baud rate generator output) Parameter Transfer rate Symbol Conditions MIN. TYP. MAX. 312.5 Unit kbps (b) UART mode (UART0, dedicated baud rate generator output): PD780102, 780103, 78F0103, 780102(A), 780103(A), and 78F0103(A) only Parameter Transfer rate Symbol Conditions MIN. TYP. MAX. 312.5 Unit kbps (c) 3-wire serial I/O mode (master mode, SCK10... internal clock output) Parameter SCK10 cycle time Symbol tKCY1 Conditions 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V 2.7 V VDD < 3.3 V SCK10 high-/low-level width tKH1, tKL1 SI10 setup time (to SCK10) SI10 hold time (from SCK10) Delay time from SCK10 to SO10 output tSIK1 tKSI1 tKSO1 C = 100 pF Note MIN. 200 240 400 tKCY1/2-10 TYP. MAX. Unit ns ns ns ns 30 30 30 ns ns ns Note C is the load capacitance of the SCK10 and SO10 output lines. (d) 3-wire serial I/O mode (slave mode, SCK10... external clock input) Parameter SCK10 cycle time SCK10 high-/low-level width Symbol tKCY2 tKH2, tKL2 SI10 setup time (to SCK10) SI10 hold time (from SCK10) Delay time from SCK10 to SO10 output tSIK2 tKSI2 tKSO2 C = 100 pF Note Conditions MIN. 400 tKCY2/2 TYP. MAX. Unit ns ns 80 50 120 ns ns ns Note C is the load capacitance of the SO10 output line. User's Manual U15836EJ4V0UD 373 CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) AC Timing Test Points (Excluding X1 Input) 0.8VDD 0.2VDD 0.8VDD 0.2VDD Test points Clock Timing 1/fXP tXL tXH X1 input VIH4 (MIN.) VIL4 (MAX.) TI Timing tTIL0 tTIH0 TI000, TI010 1/fTI5 tTIL5 tTIH5 TI50 Interrupt Request Input Timing tINTL tINTH INTP0 to INTP5 RESET Input Timing tRSL RESET 374 User's Manual U15836EJ4V0UD CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) Serial Transfer Timing 3-wire serial I/O mode: tKCYm tKLm tKHm SCK10 tSIKm tKSIm SI10 Input data tKSOm SO10 Output data Remark m = 1, 2 A/D Converter Characteristics (TA = -40 to +85C, 2.7 V VDD 5.5 V, 2.7 V AVREF VDD, VSS = AVSS = 0 V) Parameter Resolution Overall error Notes 1, 2 Symbol Conditions MIN. 10 TYP. 10 0.2 0.3 MAX. 10 0.4 0.6 100 100 0.4 0.6 0.4 0.6 2.5 4.5 1.5 2.0 Unit bit %FSR %FSR 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V Conversion time tCONV 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V 14 17 s s %FSR %FSR %FSR %FSR LSB LSB LSB LSB V Zero-scale error Notes 1, 2 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V Full-scale error Notes 1, 2 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V Integral non-linearity error Note 1 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V Differential non-linearity error Note 1 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V Analog input voltage VAIN AVSS AVREF Notes 1. 2. Excludes quantization error (1/2 LSB). This value is indicated as a ratio (%FSR) to the full-scale value. User's Manual U15836EJ4V0UD 375 CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) POC Circuit Characteristics (TA = -40 to +85C) Parameter Detection voltage Symbol VPOC0 VPOC1 Power supply rise time tPTH Conditions Mask option = 3.5 V Note 1 MIN. 3.3 2.7 0.0015 0.002 TYP. 3.5 2.85 MAX. 3.7 3.0 Unit V V ms ms Mask option = 2.85 V VDD: 0 V 2.7 V VDD: 0 V 3.3 V Note 2 Response delay time 1 Note 3 tPTHD When power supply rises, after reaching detection voltage (MAX.) 3.0 ms Response delay time 2 Minimum pulse width Note 3 tPD tPW When VDD falls 0.2 1.0 ms ms Notes 1. 2. 3. When flash memory version PD78F0103M5, 78F0103M6, 78F0103M5(A), or 78F0103M6(A) is used When flash memory version PD78F0103M3, 78F0103M4, 78F0103M3(A), or 78F0103M4(A) is used Time required from voltage detection to reset release. POC Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tPW tPTH tPTHD tPD Time 376 User's Manual U15836EJ4V0UD CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) LVI Circuit Characteristics (TA = -40 to +85C) Parameter Detection voltage Symbol VLVI0 VLVI1 VLVI2 VLVI3 VLVI4 VLVI5 VLVI6 Response time Note 1 Conditions MIN. 4.1 3.9 3.7 3.5 3.3 3.15 2.95 TYP. 4.3 4.1 3.9 3.7 3.5 3.3 3.1 0.2 MAX. 4.5 4.3 4.1 3.9 3.7 3.45 3.25 2.0 Unit V V V V V V V ms ms tLD tLW 0.2 Minimum pulse width Note 2 Reference voltage stabilization wait tLWAIT0 time Note 3 0.5 2.0 ms Operation stabilization wait time tLWAIT1 0.1 0.2 ms Notes 1. 2. Time required from voltage detection to interrupt output or internal reset output. Time required from setting LVIE to 1 to reference voltage stabilization when POC-OFF is selected by mask option (for the flash memory version, when the PD78F0103M1, 78F0103M2, 78F0103M1(A), or 78F0103M2(A) is used). 3. Time required from setting LVION to 1 to operation stabilization. Remarks 1. VLVI0 > VLVI1 > VLVI2 > VLVI3 > VLVI4 > VLVI5 > VLVI6 2. VPOCn < VLVIm (n = 0 or 1, m = 0 to 6) LVI Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tLW tWAIT0 tWAIT1 tLD LVIE 1 LVION 1 Time Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C) Parameter Data retention supply voltage Symbol VDDDR Note Conditions When POC-OFF is selected by mask option MIN. 1.6 TYP. MAX. 5.5 Unit V Release signal set time tSREL 0 s Note When flash memory version PD78F0103M1, 78F0103M2, 78F0103M1(A), or 78F0103M2(A) is used User's Manual U15836EJ4V0UD 377 CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) Flash Memory Programming Characteristics: PD78F0103, 78F0103(A) (TA = +10 to +60C, 2.7 V VDD 5.5 V, 2.7 V AVREF VDD, VSS = AVSS = 0 V) (1) Write erase characteristics Parameter VPP supply voltage VDD supply current VPP supply current Step erase time Note 1 Symbol VPP2 IDD IPP Ter Tera Twb Cwb Conditions During flash memory programming When VPP = VPP2, fXP = 10 MHz, VDD = 5.5 V VPP = VPP2 MIN. 9.7 TYP. 10.0 MAX. 10.3 37 100 Unit V mA mA s s/chip ms Times 0.199 When step erase time = 0.2 s 49.4 When writeback time = 50 ms 0.2 0.201 20 Overall erase time Writeback time Note 2 Note 3 50 50.6 60 Number of writebacks per 1 writeback command Note 4 Number of erases/writebacks Step write time Note 5 Cerwb Twr 48 When step write time = 50 s (1 word = 1 byte) 1 erase + 1 write after erase = 1 rewrite 48 50 16 52 520 Times s s Times/ area Overall write time per word Note 6 Twrw Number of rewrites per chip Note 7 Cerwr 20 Notes 1. 2. 3. 4. 5. 6. 7. The recommended setting value of the step erase time is 0.2 s. The prewrite time before erasure and the erase verify time (writeback time) are not included. The recommended setting value of the writeback time is 50 ms. Writeback is executed once by the issuance of the writeback command. Therefore, the number of retries must be the maximum value minus the number of commands issued. The recommended setting value of the step write time is 50 s. The actual write time per word is 100 s longer. The internal verify time during or after a write is not included. When a product is first written after shipment, "erase write" and "write only" are both taken as one rewrite. Example: P: Write, E: Erase Shipped product P E P E P: 3 rewrites Shipped product E P E P E P: 3 rewrites Remark The range of the operating clock during flash memory programming is the same as the range during normal operation. 378 User's Manual U15836EJ4V0UD CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS) (2) Serial write operation characteristics Parameter Set time from VDD to VPP Symbol tDP Conditions MIN. 10 10 2 TYP. MAX. Unit s s ms Release time from VPP to RESET tPR VPP pulse input start time from RESET VPP pulse high-/low-level width VPP pulse input end time from RESET VPP pulse low-level input voltage VPP pulse high-level input voltage VPPL VPPH tPW tRPE tRP 8 14 s ms 0.8VDD 9.7 10.0 1.2VDD 10.3 V V Flash Write Mode Setting Timing VDD VDD 0V VPPH VPP VPPL 0V tPR tRPE VDD RESET (input) 0V tPW tDP tRP tPW User's Manual U15836EJ4V0UD 379 CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) Target products: PD780101(A1), 780102(A1), 780103(A1), 78F0103(A1) Absolute Maximum Ratings (TA = 25C) Parameter Supply voltage Symbol VDD VSS AVREF AVSS VPP Input voltage VI1 VI2 Output voltage Analog input voltage Output current, high VO VAN IOH Per pin Total of pins P30 to P33, P120 P00 to P03, P10 to P17, P130 Total of all pins Output current, low IOL Per pin Total of all pins P30 to P33, P120 P00 to P03, P10 to P17, P130 Total of all pins Operating ambient temperature TA Conditions Ratings -0.3 to +6.5 -0.3 to +0.3 -0.3 to VDD + 0.3 -0.3 to +0.3 Note 1 Unit V V V V V Note 1 PD78F0103(A1) only Note 2 P00 to P03, P10 to P17, P20 to P23, P30 to P33, P120, P130, X1, X2, RESET VPP in flash programming mode (PD78F0103(A1) only) -0.3 to +10.5 -0.3 to VDD + 0.3 -0.3 to +10.5 -0.3 to VDD + 0.3 Note 1 V V V Note 1 AVSS - 0.3 to AVREF + 0.3 Note 1 and -0.3 to VDD + 0.3 -8 -24 -24 -40 16 28 28 48 -40 to +110 -40 to +105 -10 to +85 -65 to +150 -40 to +125 V mA mA mA mA mA mA mA mA C PD780101(A1), 780102(A1), 780103(A1) PD78F0103(A1) In normal operation mode In flash memory programming Storage temperature Tstg PD780101(A1), 780102(A1), 780103(A1) C PD78F0103(A1) Note 1. Must be 6.5 V or lower. (Refer to Note 2 on the next page.) Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 380 User's Manual U15836EJ4V0UD CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) Note 2. Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash memory is written. * When supply voltage rises VPP must exceed VDD 10 s or more after VDD has reached the lower-limit value (3.3 V) of the operating voltage range (see a in the figure below). * When supply voltage drops VDD must be lowered 10 s or more after VPP falls below the lower-limit value (3.3 V) of the operating voltage range of VDD (see b in the figure below). 3.3 V 0V a b VDD VPP 3.3 V 0V User's Manual U15836EJ4V0UD 381 CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) X1 Oscillator Characteristics (TA = -40 to +110CNote 1, 3.3 V VDD 5.5 V, 3.3 V AVREF VDD, VSS = AVSS = 0 V) Resonator Ceramic resonator Recommended Circuit Parameter Oscillation frequency (fXP) Note 2 Conditions 4.5 V VDD 5.5 V 4.0 V VDD < 4.5 V 3.3 V VDD < 4.0 V MIN. 2.0 2.0 2.0 TYP. MAX. 10 8.38 5.0 Unit MHz VSS X1 X2 C1 C2 Crystal resonator VSS X1 X2 Oscillation frequency (fXP) Note 2 4.5 V VDD 5.5 V 4.0 V VDD < 4.5 V 3.3 V VDD < 4.0 V 2.0 2.0 2.0 10 8.38 5.0 MHz C1 C2 External clock X1 input frequency 4.5 V VDD 5.5 V 4.0 V VDD < 4.5 V 3.3 V VDD < 4.0 V 2.0 2.0 2.0 46 56 96 10 8.38 5.0 500 500 500 MHz X1 X2 (fXP) Note 2 X1 input high-/lowlevel width (tXH, tXL) 4.5V VDD 5.5 V 4.0 V VDD < 4.5 V 3.3 V VDD < 4.0 V ns Notes 1. TA = -40 to +110C: PD780101(A1), 780102(A1), 780103(A1) TA = -40 to +105C: PD78F0103(A1) 2. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Caution When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. Ring-OSC Oscillator Characteristics (TA = -40 to +110CNote, 3.3 V VDD 5.5 V, 3.3 V AVREF VDD, VSS = AVSS = 0 V) Resonator On-chip Ring-OSC oscillator Parameter Oscillation frequency (fR) Conditions MIN. 120 TYP. 240 MAX. 490 Unit kHz Note TA = -40 to +110C: PD780101(A1), 780102(A1), 780103(A1) TA = -40 to +105C: PD78F0103(A1) 382 User's Manual U15836EJ4V0UD CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) DC Characteristics (1/4): PD78F0103(A1) (TA = -40 to +105C, 3.3 V VDD 5.5 V, 3.3 V AVREF VDD, VSS = AVSS = 0 V) Parameter Output current, high Symbol IOH Per pin Total of P30 to P33, P120 Conditions 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V Output current, low IOL Per pin Total of P30 to P33, P120 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V Input voltage, high VIH1 VIH2 VIH3 VIH4 Input voltage, low VIL1 VIL2 VIL3 VIL4 Output voltage, high VOH P12, P13, P15 0.7VDD MIN. TYP. MAX. -4 -20 -20 -25 -8 8 24 24 30 8 VDD VDD AVREF VDD 0.3VDD 0.2VDD 0.3AVREF 0.4 Unit mA mA mA mA mA mA mA mA mA mA V V V V V V V V V V V 1.3 1.3 0.4 10 10 20 -10 -20 10 -10 10 0 30 120 0.2VDD V V V Total of P00 to P03, P10 to P17, P130 4.0 V VDD 5.5 V Total of all pins Total of P00 to P03, P10 to P17, P130 4.0 V VDD 5.5 V Total of all pins P00 to P03, P10, P11, P14, P16, P17, P30 to P33, P120, 0.8VDD RESET P20 to P23 X1, X2 P12, P13, P15 P00 to P03, P10, P11, P14, P16, P17, P30 to P33, P120, RESET P20 to P23 X1, X2 Total of P30 to P33, P120 pins IOH = -20 mA Total of P00 to P03, P10 to P17, P130 pins IOH = -20 mA IOH = -100 A 4.0 V VDD 5.5 V, IOH = -4 mA 4.0 V VDD 5.5 V, IOH = -4 mA 3.3 V VDD < 4.0 V 4.0 V VDD 5.5 V, IOL = 8 mA 4.0 V VDD 5.5 V, IOL = 8 mA 3.3 V VDD < 4.0 V P00 to P03, P10 to P17, P30 to P33, P120, RESET P20 to P23 X1, X2 Note 2 Note 1 Note 1 0.7AVREF VDD - 0.5 0 0 0 0 VDD - 1.0 VDD - 1.0 VDD - 0.5 Output voltage, low VOL Total of P30 to P33, P120 pins IOL = 24 mA Total of P00 to P03, P10 to P17, P130 pins IOL = 24 mA IOL = 400 A Input leakage current, high ILIH1 VI = VDD VI = AVREF A A A A A A A k V ILIH2 Input leakage current, low ILIL1 ILIL2 Output leakage current, high ILOH Output leakage current, low Pull-up resistance value VPP supply voltage ILOL R VPP1 VI = VDD VI = 0 V P00 to P03, P10 to P17, P20 to P23, P30 to P33, P120, RESET X1, X2 Note 2 VO = VDD VO = 0 V VI = 0 V In normal operation mode Notes 1. When used as a digital input port, set AVREF = VDD. 2. When the inverse level of X1 is input to X2. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U15836EJ4V0UD 383 CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) DC Characteristics (2/4): PD780101(A1), 780102(A1), 780103(A1) (TA = -40 to +110C, 3.3 V VDD 5.5 V, 3.3 V AVREF VDD, VSS = AVSS = 0 V) Parameter Output current, high Symbol IOH Per pin Total of P30 to P33, P120 Conditions 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V Output current, low IOL Per pin Total of P30 to P33, P120 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V Input voltage, high VIH1 VIH2 VIH3 VIH4 Input voltage, low VIL1 VIL2 VIL3 VIL4 Output voltage, high VOH P12, P13, P15 0.7VDD MIN. TYP. MAX. -4 -20 -20 -32 -8 8 24 24 40 8 VDD VDD AVREF VDD 0.3VDD 0.2VDD 0.3AVREF 0.4 Unit mA mA mA mA mA mA mA mA mA mA V V V V V V V V V V V 1.3 1.3 0.4 10 10 20 -10 -20 10 -10 10 30 120 V V V Total of P00 to P03, P10 to P17, P130 4.0 V VDD 5.5 V Total of all pins Total of P00 to P03, P10 to P17, P130 4.0 V VDD 5.5 V Total of all pins P00 to P03, P10, P11, P14, P16, P17, P30 to P33, P120, 0.8VDD RESET P20 to P23 X1, X2 P12, P13, P15 P00 to P03, P10, P11, P14, P16, P17, P30 to P33, P120, RESET P20 to P23 X1, X2 Total of P30 to P33, P120 pins IOH = -20 mA Total of P00 to P03, P10 to P17, P130 pins IOH = -20 mA IOH = -100 A 4.0 V VDD 5.5 V, IOH = -4 mA 4.0 V VDD 5.5 V, IOH = -4 mA 3.3 V VDD < 4.0 V 4.0 V VDD 5.5 V, IOL = 8 mA 4.0 V VDD 5.5 V, IOL = 8 mA 3.3 V VDD < 4.0 V P00 to P03, P10 to P17, P30 to P33, P120, RESET P20 to P23 X1, X2 Note 2 Note 1 0.7AVREF VDD - 0.5 0 0 0 0 VDD - 1.0 VDD - 1.0 VDD - 0.5 Output voltage, low VOL Total of P30 to P33, P120 pins IOL = 24 mA Total of P00 to P03, P10 to P17, P130 pins IOL = 24 mA IOL = 400 A Input leakage current, high ILIH1 VI = VDD VI = AVREF A A A A A A A k ILIH2 Input leakage current, low ILIL1 ILIL2 Output leakage current, high ILOH Output leakage current, low Pull-up resistance value ILOL R VI = VDD VI = 0 V P00 to P03, P10 to P17, P20 to P23, P30 to P33, P120, RESET X1, X2 Note 2 VO = VDD VO = 0 V VI = 0 V Notes 1. When used as a digital input port, set AVREF = VDD. 2. When the inverse level of X1 is input to X2. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 384 User's Manual U15836EJ4V0UD CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) DC Characteristics (3/4): PD78F0103(A1) (TA = -40 to +105C, 3.3 V VDD 5.5 V, 3.3 V AVREF VDD, VSS = AVSS = 0 V) Parameter Supply current Note 1 Symbol IDD1 X1 crystal oscillation operating mode IDD2 Note 2 Conditions fXP = 10 MHz, VDD = 5.0 V 10% Note 3 MIN. TYP. MAX. Unit 11.6 Note 4 When A/D converter is stopped When A/D converter is operating 20.6 22.6 mA mA 12.6 X1 crystal oscillation HALT mode fXP = 10 MHz, VDD = 5.0 V 10% When peripheral functions are stopped When peripheral functions are operating 1.4 3.9 6.6 mA mA IDD3 Ring-OSC operating mode Note 5 VDD = 5.0 V 10% 0.37 2.61 mA IDD4 STOP mode VDD = 5.0 V 10% POC: OFF, RING: OFF POC: OFF, RING: ON POC: ON Note 6 0.1 14 3.5 1100 1200 1100 A A A A , RING: OFF , RING: ON POC: ON Note 6 17.5 1200 Notes 1. 2. 3. 4. 5. 6. Total current flowing through the internal power supply (VDD). Peripheral operation current is included (however, the current that flows through the pull-up resistors of ports is not included). IDD1 includes peripheral operation current. When PCC = 00H. Total current flowing through VDD and AVREF pins. When X1 oscillator is stopped. Including when LVIE (bit 4 of LVIM) = 1 in the PD78F0103M1(A1) and 78F0103M2(A1). User's Manual U15836EJ4V0UD 385 CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) DC Characteristics (4/4): PD780101(A1), 780102(A1), 780103(A1) (TA = -40 to +110C, 3.3 V VDD 5.5 V, 3.3 V AVREF VDD, VSS = AVSS = 0 V) Parameter Supply current Note 1 Symbol IDD1 X1 crystal fXP = 10 MHz, oscillation VDD = 5.0 V 10% operating mode IDD2 Note 2 Conditions When A/D converter is stopped Note 3 MIN. TYP. MAX. Unit 6 Note 4 11.7 13.7 mA mA When A/D converter is operating 7 X1 crystal fXP = 10 MHz, oscillation VDD = 5.0 V 10% HALT mode Ring-OSC VDD = 5.0 V 10% operating mode Note 5 When peripheral functions are stopped When peripheral functions are operating 1.3 3.4 5.6 mA mA IDD3 0.18 1.52 mA IDD4 STOP mode VDD = 5.0 V 10% POC: OFF, RING: OFF POC: OFF, RING: ON POC: ON Note 6 0.1 14 3.5 17.5 800 900 800 900 A A A A , RING: OFF , RING: ON POC: ON Note 6 Notes 1. 2. 3. 4. 5. 6. Total current flowing through the internal power supply (VDD). Peripheral operation current is included (however, the current that flows through the pull-up resistors of ports is not included). IDD1 includes peripheral operation current. When PCC = 00H. Total current flowing through VDD and AVREF pins. When X1 oscillator is stopped. Including when LVIE (bit 4 of LVIM) = 1 with POC-OFF selected by a mask option. 386 User's Manual U15836EJ4V0UD CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) AC Characteristics (1) Basic operation (TA = -40 to +110C Parameter Instruction cycle (minimum instruction execution time) Symbol TCY X1 input clock Note 1 , 3.3 V VDD 5.5 V, 3.3 V AVREF VDD, VSS = AVSS = 0 V) Conditions 4.5 V VDD 5.5 V 4.0 V VDD < 4.5 V 3.3 V VDD < 4.0 V MIN. 0.2 0.238 0.4 4.09 2/fsam+ Note 2 0.1 2/fsam+ Note 2 0.2 10 5 50 100 1 10 ns ns 8.33 TYP. MAX. 16 16 16 16.67 Unit s s s s s s MHz Ring-OSC clock TI000, TI010 input high-level width, low-level width tTIH0, tTIL0 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V TI50 input frequency fTI5 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V TI50 input high-level width, low- tTIH5, level width tTIL5 Interrupt input high-level width, low-level width RESET low-level width tINTH, tINTL tRSL 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V s s Notes 1. TA = -40 to +110C: PD780101(A1), 780102(A1), 780103(A1) TA = -40 to +105C: PD78F0103(A1) 2. Selection of fsam = fXP, fXP/4, fXP/256 is possible using bits 0 and 1 (PRM000, PRM001) of prescaler mode register 00 (PRM00). Note that when selecting the TI000 valid edge as the count clock, fsam = fXP. TCY vs. VDD (X1 Input Clock Operation) 20.0 16.0 10.0 Cycle time TCY [ s] 5.0 2.0 1.0 Guaranteed operation range 0.4 0.238 0.2 0.1 0 1.0 2.0 3.0 3.3 4.0 4.5 5.0 5.5 6.0 Supply voltage VDD [V] User's Manual U15836EJ4V0UD 387 CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) (2) Serial interface (TA = -40 to +110CNote, 3.3 V VDD 5.5 V, 3.3 V AVREF VDD, VSS = AVSS = 0 V) Note TA = -40 to +110C: PD780101(A1), 780102(A1), 780103(A1) TA = -40 to +105C: PD78F0103(A1) (a) UART mode (UART6, dedicated baud rate generator output) Parameter Transfer rate Symbol Conditions MIN. TYP. MAX. 312.5 Unit kbps (b) UART mode (UART0, dedicated baud rate generator output): PD780102(A1), 780103(A1), and 78F0103(A1) only Parameter Transfer rate Symbol Conditions MIN. TYP. MAX. 312.5 Unit kbps (c) 3-wire serial I/O mode (master mode, SCK10... internal clock output) Parameter SCK10 cycle time Symbol tKCY1 Conditions 4.5 V VDD 5.5 V 4.0 V VDD < 4.5 V 3.3 V VDD < 4.0 V SCK10 high-/low-level width tKH1, tKL1 SI10 setup time (to SCK10) SI10 hold time (from SCK10) Delay time from SCK10 to SO10 output tSIK1 tKSI1 tKSO1 C = 100 pF Note MIN. 200 240 400 tKCY1/2-10 TYP. MAX. Unit ns ns ns ns 30 30 30 ns ns ns Note C is the load capacitance of the SCK10 and SO10 output lines. (d) 3-wire serial I/O mode (slave mode, SCK10... external clock input) Parameter SCK10 cycle time SCK10 high-/low-level width Symbol tKCY2 tKH2, tKL2 SI10 setup time (to SCK10) SI10 hold time (from SCK10) Delay time from SCK10 to SO10 output tSIK2 tKSI2 tKSO2 C = 100 pF Note Conditions MIN. 400 tKCY2/2 TYP. MAX. Unit ns ns 80 50 120 ns ns ns Note C is the load capacitance of the SO10 output line. 388 User's Manual U15836EJ4V0UD CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) AC Timing Test Points (Excluding X1 Input) 0.8VDD 0.2VDD 0.8VDD 0.2VDD Test points Clock Timing 1/fXP tXL tXH X1 input VIH4 (MIN.) VIL4 (MAX.) TI Timing tTIL0 tTIH0 TI000, TI010 1/fTI5 tTIL5 tTIH5 TI50 Interrupt Request Input Timing tINTL tINTH INTP0 to INTP5 RESET Input Timing tRSL RESET User's Manual U15836EJ4V0UD 389 CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) Serial Transfer Timing 3-wire serial I/O mode: tKCYm tKLm tKHm SCK10 tSIKm tKSIm SI10 Input data tKSOm SO10 Output data Remark m = 1, 2 A/D Converter Characteristics (TA = -40 to +110CNote 1, 3.3 V VDD 5.5 V, 3.3 V AVREF VDD, VSS = AVSS = 0 V) Parameter Resolution Overall error Notes 2, 3 Symbol Conditions MIN. 10 TYP. 10 0.2 0.3 MAX. 10 0.6 0.8 60 60 0.6 0.8 0.6 0.8 4.5 6.5 2.0 2.5 Unit bit %FSR %FSR 4.0 V AVREF 5.5 V 3.3 V AVREF < 4.0 V Conversion time tCONV 4.0 V AVREF 5.5 V 3.3 V AVREF < 4.0 V 14 19 s s %FSR %FSR %FSR %FSR LSB LSB LSB LSB V Zero-scale error Notes 2, 3 4.0 V AVREF 5.5 V 3.3 V AVREF < 4.0 V Full-scale error Notes 2, 3 4.0 V AVREF 5.5 V 3.3 V AVREF < 4.0 V Integral non-linearity error Note 2 4.0 V AVREF 5.5 V 3.3 V AVREF < 4.0 V Differential non-linearity error Note 2 4.0 V AVREF 5.5 V 3.3 V AVREF < 4.0 V Analog input voltage VAIN AVSS AVREF Notes 1. TA = -40 to +110C: PD780101(A1), 780102(A1), 780103(A1) TA = -40 to +105C: PD78F0103(A1) 2. 3. Excludes quantization error (1/2 LSB). This value is indicated as a ratio (%FSR) to the full-scale value. 390 User's Manual U15836EJ4V0UD CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) POC Circuit Characteristics (TA = -40 to +110CNote 1) Parameter Detection voltage Power supply rise time Response delay time 1 Note 3 Symbol VPOC0 tPTH tPTHD Conditions Mask option = 3.5 V VDD: 0 V 3.3 V When power supply rises, after reaching detection voltage (MAX.) Note 2 MIN. 3.3 0.002 TYP. 3.5 MAX. 3.72 Unit V ms 3.0 ms Response delay time 2 Minimum pulse width Note 3 tPD tPW When VDD falls 0.2 1.0 ms ms Notes 1. TA = -40 to +110C: PD780101(A1), 780102(A1), 780103(A1) TA = -40 to +105C: PD78F0103(A1) 2. 3. When flash memory version PD78F0103M5(A1) or 78F0103M6(A1) is used Time required from voltage detection to reset release. POC Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tPW tPTH tPTHD tPD Time User's Manual U15836EJ4V0UD 391 CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) LVI Circuit Characteristics (TA = -40 to +110CNote 1) Parameter Detection voltage Symbol VLVI0 VLVI1 VLVI2 VLVI3 VLVI4 Response time Note 2 Conditions MIN. 4.1 3.9 3.7 3.5 3.3 TYP. 4.3 4.1 3.9 3.7 3.5 0.2 MAX. 4.52 4.32 4.12 3.92 3.72 2.0 Unit V V V V V ms ms tLD tLW 0.2 Minimum pulse width Note 3 Reference voltage stabilization wait tLWAIT0 time Note 4 0.5 2.0 ms Operation stabilization wait time tLWAIT1 0.1 0.2 ms Notes 1. TA = -40 to +110C: PD780101(A1), 780102(A1), 780103(A1) TA = -40 to +105C: PD78F0103(A1) 2. 3. 4. Time required from voltage detection to interrupt output or internal reset output. Time required from setting LVIE to 1 to reference voltage stabilization when POC-OFF is selected by mask option (for the flash memory version, when the PD78F0103M1(A1) or 78F0103M2(A1) is used). Time required from setting LVION to 1 to operation stabilization. Remarks 1. VLVI0 > VLVI1 > VLVI2 > VLVI3 > VLVI4 2. VPOCn < VLVIm (n = 0 or 1, m = 0 to 4) LVI Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tLW tWAIT0 tWAIT1 tLD LVIE 1 LVION 1 Time Note 1 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +110C Parameter Data retention supply voltage Symbol VDDDR Note 2 ) Unit V Conditions When POC-OFF is selected by mask option MIN. 2.0 TYP. MAX. 5.5 Release signal set time tSREL 0 s Notes 1. TA = -40 to +110C: PD780101(A1), 780102(A1), 780103(A1) TA = -40 to +105C: PD78F0103(A1) 2. When flash memory version PD78F0103M1(A1) or 78F0103M2(A1) is used 392 User's Manual U15836EJ4V0UD CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) Flash Memory Programming Characteristics: PD78F0103(A1) (TA = +10 to +60C, 3.3 V VDD 5.5 V, 3.3 V AVREF VDD, VSS = AVSS = 0 V) (1) Write erase characteristics Parameter VPP supply voltage VDD supply current VPP supply current Step erase time Note 1 Symbol VPP2 IDD IPP Ter Tera Twb Cwb Conditions During flash memory programming When VPP = VPP2, fXP = 10 MHz, VDD = 5.5 V VPP = VPP2 MIN. 9.7 TYP. 10.0 MAX. 10.3 37 100 Unit V mA mA s s/chip ms Times 0.199 When step erase time = 0.2 s 49.4 When writeback time = 50 ms 0.2 0.201 20 Overall erase time Writeback time Note 2 Note 3 50 50.6 60 Number of writebacks per 1 writeback command Note 4 Number of erases/writebacks Step write time Note 5 Cerwb Twr 48 When step write time = 50 s (1 word = 1 byte) 1 erase + 1 write after erase = 1 rewrite 48 50 16 52 520 Times s s Times/ area Overall write time per word Note 6 Twrw Number of rewrites per chip Note 7 Cerwr 20 Notes 1. 2. 3. 4. 5. 6. 7. The recommended setting value of the step erase time is 0.2 s. The prewrite time before erasure and the erase verify time (writeback time) are not included. The recommended setting value of the writeback time is 50 ms. Writeback is executed once by the issuance of the writeback command. Therefore, the number of retries must be the maximum value minus the number of commands issued. The recommended setting value of the step write time is 50 s. The actual write time per word is 100 s longer. The internal verify time during or after a write is not included. When a product is first written after shipment, "erase write" and "write only" are both taken as one rewrite. Example: P: Write, E: Erase Shipped product P E P E P: 3 rewrites Shipped product E P E P E P: 3 rewrites Remark The range of the operating clock during flash memory programming is the same as the range during normal operation. User's Manual U15836EJ4V0UD 393 CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) (2) Serial write operation characteristics Parameter Set time from VDD to VPP Symbol tDP Conditions MIN. 10 10 2 TYP. MAX. Unit s s ms Release time from VPP to RESET tPR VPP pulse input start time from RESET VPP pulse high-/low-level width VPP pulse input end time from RESET VPP pulse low-level input voltage VPP pulse high-level input voltage VPPL VPPH tPW tRPE tRP 8 14 s ms 0.8VDD 9.7 10.0 1.2VDD 10.3 V V Flash Write Mode Setting Timing VDD VDD 0V VPPH VPP VPPL 0V tPR tRPE VDD RESET (input) 0V tPW tDP tRP tPW 394 User's Manual U15836EJ4V0UD CHAPTER 25 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) Target products: PD780101(A2), 780102(A2), 780103(A2) Absolute Maximum Ratings (TA = 25C) Parameter Supply voltage Symbol VDD VSS AVREF AVSS Input voltage Output voltage Analog input voltage Output current, high VI1 VO VAN IOH Per pin Total of pins P30 to P33, P120 P00 to P03, P10 to P17, P130 Total of all pins Output current, low IOL Per pin Total of all pins P30 to P33, P120 P00 to P03, P10 to P17, P130 Total of all pins Operating ambient temperature Storage temperature TA Tstg In normal operation mode P00 to P03, P10 to P17, P20 to P23, P30 to P33, P120, P130, X1, X2, RESET Conditions Ratings -0.3 to +6.5 -0.3 to +0.3 -0.3 to VDD + 0.3 -0.3 to +0.3 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 Note Note Unit V V V V V V Note Note AVSS - 0.3 to AVREF + 0.3 Note and -0.3 to VDD + 0.3 -7 -21 -21 -35 14 24.5 24.5 42 -40 to +125 -65 to +150 V mA mA mA mA mA mA mA mA C C Note Must be 6.5 V or lower. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U15836EJ4V0UD 395 CHAPTER 25 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) X1 Oscillator Characteristics (TA = -40 to +125C, 3.3 V VDD 5.5 V, 3.3 V AVREF VDD, VSS = AVSS = 0 V) Resonator Ceramic resonator Recommended Circuit Parameter Oscillation frequency (fXP) Note Conditions 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V MIN. 2.0 2.0 TYP. MAX. 8.38 5.0 Unit MHz VSS X1 X2 C1 C2 Crystal resonator VSS X1 X2 Oscillation frequency (fXP) Note 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V 2.0 2.0 8.38 5.0 MHz C1 C2 External clock X1 input frequency 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V 2.0 2.0 8.38 5.0 MHz X1 X2 (fXP) Note X1 input high-/lowlevel width (tXH, tXL) 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V 56 96 500 500 ns Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Caution When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. Ring-OSC Oscillator Characteristics (TA = -40 to +125C, 3.3 V VDD 5.5 V, 3.3 V AVREF VDD, VSS = AVSS = 0 V) Resonator On-chip Ring-OSC oscillator Parameter Oscillation frequency (fR) Conditions MIN. 120 TYP. 240 MAX. 495 Unit kHz 396 User's Manual U15836EJ4V0UD CHAPTER 25 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) DC Characteristics (1/2) (TA = -40 to +125C, 3.3 V VDD 5.5 V, 3.3 V AVREF VDD, VSS = AVSS = 0 V) Parameter Output current, high Symbol IOH Per pin Total of P30 to P33, P120 Conditions 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V Output current, low IOL Per pin Total of P30 to P33, P120 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V Input voltage, high VIH1 VIH2 VIH3 VIH4 Input voltage, low VIL1 VIL2 VIL3 VIL4 Output voltage, high VOH P12, P13, P15 0.7VDD MIN. TYP. MAX. -3.5 -17.5 -17.5 -28 -7 7 21 21 35 7 VDD VDD AVREF VDD 0.3VDD 0.2VDD 0.3AVREF 0.4 Unit mA mA mA mA mA mA mA mA mA mA V V V V V V V V V V V 1.3 1.3 0.4 10 10 20 -10 -20 10 -10 10 30 120 V V V Total of P00 to P03, P10 to P17, P130 4.0 V VDD 5.5 V Total of all pins Total of P00 to P03, P10 to P17, P130 4.0 V VDD 5.5 V Total of all pins P00 to P03, P10, P11, P14, P16, P17, P30 to P33, P120, 0.8VDD RESET P20 to P23 X1, X2 P12, P13, P15 P00 to P03, P10, P11, P14, P16, P17, P30 to P33, P120, RESET P20 to P23 X1, X2 Total of P30 to P33, P120 pins IOH = -17.5 mA Total of P00 to P03, P10 to P17, P130 pins IOH = -17.5 mA IOH = -100 A 4.0 V VDD 5.5 V, IOH = -3.5 mA 4.0 V VDD 5.5 V, IOH = -3.5 mA 3.3 V VDD < 4.0 V 4.0 V VDD 5.5 V, IOL = 7 mA 4.0 V VDD 5.5 V, IOL = 7 mA 3.3 V VDD < 4.0 V P00 to P03, P10 to P17, P30 to P33, P120, RESET P20 to P23 X1, X2 Note 2 Note 1 0.7AVREF VDD - 0.5 0 0 0 0 VDD - 1.0 VDD - 1.0 VDD - 0.5 Output voltage, low VOL Total of P30 to P33, P120 pins IOL = 21 mA Total of P00 to P03, P10 to P17, P130 pins IOL = 21 mA IOL = 400 A Input leakage current, high ILIH1 VI = VDD VI = AVREF A A A A A A A k ILIH2 Input leakage current, low ILIL1 ILIL2 Output leakage current, high ILOH Output leakage current, low Pull-up resistance value ILOL R VI = VDD VI = 0 V P00 to P03, P10 to P17, P20 to P23, P30 to P33, P120, RESET X1, X2 Note 2 VO = VDD VO = 0 V VI = 0 V Notes 1. When used as a digital input port, set AVREF = VDD. 2. When the inverse level of X1 is input to X2. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U15836EJ4V0UD 397 CHAPTER 25 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) DC Characteristics (2/2) (TA = -40 to +125C, 3.3 V VDD 5.5 V, 3.3 V AVREF VDD, VSS = AVSS = 0 V) Parameter Supply current Note 1 Symbol IDD1 X1 crystal fXP = 8.38 MHz, oscillation VDD = 5.0 V 10% operating mode IDD2 Note 2 Conditions When A/D converter is stopped Note 3 MIN. TYP. MAX. Unit 5.2 Note 4 10.6 12.6 mA mA When A/D converter is operating 6.2 X1 crystal fXP = 8.38 MHz, oscillation VDD = 5.0 V 10% HALT mode Ring-OSC VDD = 5.0 V 10% operating mode Note 5 When peripheral functions are stopped When peripheral functions are operating 1.2 3.6 5.5 mA mA IDD3 0.18 1.92 mA IDD4 STOP mode VDD = 5.0 V 10% POC: OFF, RING: OFF POC: OFF, RING: ON POC: ON Note 6 0.1 14 3.5 1200 1300 1200 A A A A , RING: OFF , RING: ON POC: ON Note 6 17.5 1300 Notes 1. 2. 3. 4. 5. 6. Total current flowing through the internal power supply (VDD). Peripheral operation current is included (however, the current that flows through the pull-up resistors of ports is not included). IDD1 includes peripheral operation current. When PCC = 00H. Total current flowing through VDD and AVREF pins. When X1 oscillator is stopped. Including when LVIE (bit 4 of LVIM) = 1 with POC-OFF selected by a mask option. 398 User's Manual U15836EJ4V0UD CHAPTER 25 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) AC Characteristics (1) Basic operation (TA = -40 to +125C, 3.3 V VDD 5.5 V, 3.3 V AVREF VDD, VSS = AVSS = 0 V) Parameter Instruction cycle (minimum instruction execution time) Symbol TCY X1 input clock Conditions 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V Ring-OSC clock TI000, TI010 input high-level width, low-level width tTIH0, tTIL0 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V TI50 input frequency fTI5 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V TI50 input high-level width, low- tTIH5, level width tTIL5 Interrupt input high-level width, low-level width RESET low-level width tINTH, tINTL tRSL 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V 59.6 100 1 10 MIN. 0.238 0.4 4.04 2/fsam+ Note 0.1 2/fsam+ Note 0.2 8.38 5 ns ns 8.33 TYP. MAX. 16 16 16.67 Unit s s s s s MHz s s Note Selection of fsam = fXP, fXP/4, fXP/256 is possible using bits 0 and 1 (PRM000, PRM001) of prescaler mode register 00 (PRM00). Note that when selecting the TI000 valid edge as the count clock, fsam = fXP. TCY vs. VDD (X1 Input Clock Operation) 20.0 16.0 10.0 Cycle time TCY [ s] 5.0 2.0 1.0 Guaranteed operation range 0.4 0.238 0.2 0.1 0 1.0 2.0 3.0 3.3 4.0 5.0 5.5 6.0 Supply voltage VDD [V] User's Manual U15836EJ4V0UD 399 CHAPTER 25 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (2) Serial interface (TA = -40 to +125C, 3.3 V VDD 5.5 V, 3.3 V AVREF VDD, VSS = AVSS = 0 V) (a) UART mode (UART6, dedicated baud rate generator output) Parameter Transfer rate Symbol Conditions MIN. TYP. MAX. 261.9 Unit kbps (b) UART mode (UART0, dedicated baud rate generator output): PD780102(A2) and 780103(A2) only Parameter Transfer rate Symbol Conditions MIN. TYP. MAX. 261.9 Unit kbps (c) 3-wire serial I/O mode (master mode, SCK10... internal clock output) Parameter SCK10 cycle time Symbol tKCY1 Conditions 4.0 V VDD 5.5 V 3.3 V VDD < 4.0 V SCK10 high-/low-level width tKH1, tKL1 SI10 setup time (to SCK10) SI10 hold time (from SCK10) Delay time from SCK10 to SO10 output tSIK1 tKSI1 tKSO1 C = 100 pF Note MIN. 240 400 tKCY1/2-10 TYP. MAX. Unit ns ns ns 30 30 30 ns ns ns Note C is the load capacitance of the SCK10 and SO10 output lines. (d) 3-wire serial I/O mode (slave mode, SCK10... external clock input) Parameter SCK10 cycle time SCK10 high-/low-level width Symbol tKCY2 tKH2, tKL2 SI10 setup time (to SCK10) SI10 hold time (from SCK10) Delay time from SCK10 to SO10 output tSIK2 tKSI2 tKSO2 C = 100 pF Note Conditions MIN. 400 tKCY2/2 TYP. MAX. Unit ns ns 80 50 120 ns ns ns Note C is the load capacitance of the SO10 output line. 400 User's Manual U15836EJ4V0UD CHAPTER 25 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) AC Timing Test Points (Excluding X1 Input) 0.8VDD 0.2VDD 0.8VDD 0.2VDD Test points Clock Timing 1/fXP tXL tXH X1 input VIH4 (MIN.) VIL4 (MAX.) TI Timing tTIL0 tTIH0 TI000, TI010 1/fTI5 tTIL5 tTIH5 TI50 Interrupt Request Input Timing tINTL tINTH INTP0 to INTP5 RESET Input Timing tRSL RESET User's Manual U15836EJ4V0UD 401 CHAPTER 25 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) Serial Transfer Timing 3-wire serial I/O mode: tKCYm tKLm tKHm SCK10 tSIKm tKSIm SI10 Input data tKSOm SO10 Output data Remark m = 1, 2 402 User's Manual U15836EJ4V0UD CHAPTER 25 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) A/D Converter Characteristics (TA = -40 to +125C, 3.3 V VDD 5.5 V, 3.3 V AVREF VDD, VSS = AVSS = 0 V) Parameter Resolution Overall error Notes 1, 2 Symbol Conditions MIN. 10 TYP. 10 0.2 0.3 MAX. 10 0.7 0.9 48 48 0.7 0.9 0.7 0.9 5.5 7.5 2.5 3.0 Unit bit %FSR %FSR 4.0 V AVREF 5.5 V 3.3 V AVREF < 4.0 V Conversion time tCONV 4.0 V AVREF 5.5 V 3.3 V AVREF < 4.0 V 16 19 s s %FSR %FSR %FSR %FSR LSB LSB LSB LSB V Zero-scale error Notes 1, 2 4.0 V AVREF 5.5 V 3.3 V AVREF < 4.0 V Full-scale error Notes 1, 2 4.0 V AVREF 5.5 V 3.3 V AVREF < 4.0 V Integral non-linearity error Note 1 4.0 V AVREF 5.5 V 3.3 V AVREF < 4.0 V Differential non-linearity error Note 1 4.0 V AVREF 5.5 V 3.3 V AVREF < 4.0 V Analog input voltage VAIN AVSS AVREF Notes 1. 2. Excludes quantization error (1/2 LSB). This value is indicated as a ratio (%FSR) to the full-scale value. POC Circuit Characteristics (TA = -40 to +125C) Parameter Detection voltage Power supply rise time Response delay time 1 Note Symbol VPOC0 tPTH tPTHD Conditions Mask option = 3.5 V VDD: 0 V 3.3 V When power supply rises, after reaching detection voltage (MAX.) MIN. 3.3 0.002 TYP. 3.5 MAX. 3.76 Unit V ms 3.0 ms Response delay time 2 Minimum pulse width Note tPD tPW When VDD falls 0.2 1.0 ms ms Note Time required from voltage detection to reset release. POC Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tPW tPTH tPTHD tPD Time User's Manual U15836EJ4V0UD 403 CHAPTER 25 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) LVI Circuit Characteristics (TA = -40 to +125C) Parameter Detection voltage Symbol VLVI0 VLVI1 VLVI2 VLVI3 VLVI4 Response time Note 1 Conditions MIN. 4.1 3.9 3.7 3.5 3.3 TYP. 4.3 4.1 3.9 3.7 3.5 0.2 MAX. 4.56 4.36 4.16 3.96 3.76 2.0 Unit V V V V V ms ms tLD tLW 0.2 Minimum pulse width Note 2 Reference voltage stabilization wait tLWAIT0 time Note 3 0.5 2.0 ms Operation stabilization wait time tLWAIT1 0.1 0.2 ms Notes 1. 2. 3. Time required from voltage detection to interrupt output or internal reset output. Time required from setting LVIE to 1 to reference voltage stabilization when POC-OFF is selected by mask option. Time required from setting LVION to 1 to operation stabilization. Remarks 1. VLVI0 > VLVI1 > VLVI2 > VLVI3 > VLVI4 2. VPOCn < VLVIm (n = 0 or 1, m = 0 to 4) LVI Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tLW tWAIT0 tWAIT1 tLD LVIE 1 LVION 1 Time Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +125C) Parameter Data retention supply voltage Symbol VDDDR Conditions When POC-OFF is selected by mask option Release signal set time tSREL 0 MIN. 2.0 TYP. MAX. 5.5 Unit V s 404 User's Manual U15836EJ4V0UD CHAPTER 26 PACKAGE DRAWING 30-PIN PLASTIC SSOP (7.62 mm (300)) 30 16 detail of lead end F G T P 1 A 15 E L U H I J S C D M M N S B K NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. ITEM A B C D E F G H I J K L M N P T U MILLIMETERS 9.850.15 0.45 MAX. 0.65 (T.P.) 0.24 +0.08 -0.07 0.10.05 1.30.1 1.2 8.10.2 6.10.2 1.00.2 0.170.03 0.5 0.13 0.10 +5 3 -3 0.25 0.60.15 S30MC-65-5A4-2 User's Manual U15836EJ4V0UD 405 CHAPTER 27 RECOMMENDED SOLDERING CONDITIONS These products should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, please contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Table 27-1. Surface Mounting Type Soldering Conditions (1/2) (1) 30-pin plastic SSOP (7.62 mm (300)) PD780101MC-xxx-5A4, 780102MC-xxx-5A4, 780103MC-xxx-5A4, PD780101MC(A)-xxx-5A4, 780102MC(A)-xxx-5A4, 780103MC(A)-xxx-5A4, PD780101MC(A1)-xxx-5A4, 780102MC(A1)-xxx-5A4, 780103MC(A1)-xxx-5A4, PD780101MC(A2)-xxx-5A4, 780102MC(A2)-xxx-5A4, 780103MC(A2)-xxx-5A4 Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: 3 times or less, Exposure limit: 7 days 10 hours) VPS Note IR35-107-3 (after that, prebake at 125C for Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: 3 times or less, Exposure limit: 7 days 10 hours) Note VP15-107-3 (after that, prebake at 125C for Wave soldering Solder bath temperature: 260C max., Time: 10 seconds max., Count: Once, Preheating temperature: 120C max. (package surface temperature), Exposure Note limit: 7 days (after that, prebake at 125C for 10 hours) WS60-107-1 Partial heating Pin temperature: 300C max., Time: 3 seconds max. (per pin row) - Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). 406 User's Manual U15836EJ4V0UD CHAPTER 27 RECOMMENDED SOLDERING CONDITIONS Table 27-1. Surface Mounting Type Soldering Conditions (2/2) (2) 30-pin plastic SSOP (7.62 mm (300)) PD78F0103M1MC-5A4, 78F0103M2MC-5A4, 78F0103M3MC-5A4, 78F0103M4MC-5A4, PD78F0103M5MC-5A4, 78F0103M6MC-5A4, 78F0103M1MC(A)-5A4, 78F0103M2MC(A)-5A4, PD78F0103M3MC(A)-5A4, 78F0103M4MC(A)-5A4, 78F0103M5MC(A)-5A4, PD78F0103M6MC(A)-5A4, 78F0103M1MC(A1)-5A4, 78F0103M2MC(A1)-5A4, PD78F0103M5MC(A1)-5A4, 78F0103M6MC(A1)-5A4 Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: 2 times or less, Exposure limit: 3 days 10 hours) VPS Note IR35-103-2 (after that, prebake at 125C for Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: 2 times or less, Exposure limit: 3 days 10 hours) Note VP15-103-2 (after that, prebake at 125C for Wave soldering Solder bath temperature: 260C max., Time: 10 seconds max., Count: Once, Preheating temperature: 120C Max. (package surface temperature), Exposure Note limit: 3 days (after that, prebake at 125C for 10 hours) WS60-103-1 Partial heating Pin temperature: 300C max., Time: 3 seconds max. (per pin row) - Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). User's Manual U15836EJ4V0UD 407 CHAPTER 28 CAUTIONS FOR WAIT 28.1 Cautions for Wait This product has two internal system buses. One is a CPU bus and the other is a peripheral bus that interfaces with the low-speed peripheral hardware. Because the clock of the CPU bus and the clock of the peripheral bus are asynchronous, unexpected illegal data may be passed if an access to the CPU conflicts with an access to the peripheral hardware. When accessing the peripheral hardware that may cause a conflict, therefore, the CPU repeatedly executes processing, until the correct data is passed. As a result, the CPU does not start the next instruction processing but waits. If this happens, the number of execution clocks of an instruction increases by the number of wait clocks (for the number of wait clocks, see Table 281). This must be noted when real-time processing is performed. 408 User's Manual U15836EJ4V0UD CHAPTER 28 CAUTIONS FOR WAIT 28.2 Peripheral Hardware That Generates Wait Table 28-1 lists the registers that issue a wait request when accessed by the CPU, and the number of CPU wait clocks. Table 28-1. Registers That Generate Wait and Number of CPU Wait Clocks Peripheral Hardware Watchdog timer Serial interface UART0 Serial interface UART6 A/D converter WDTM ASIS0 ASIS6 ADM ADS PFM PFT ADCR Register Write Read Read Write Write Write Write Read 1 to 5 clocks (when ADM.5 flag = "1") 1 to 9 clocks (when ADM.5 flag = "0") 2 Access Number of Wait Clocks 3 clocks (fixed) 1 clock (fixed) 1 clock (fixed) 2 to 5 clocks 2 to 9 clocks Note (when ADM.5 flag = "1") Note (when ADM.5 flag = "0") Note No wait cycle is generated for the CPU if the number of wait clocks calculated by the above expression is 1. Remark The clock is the CPU clock (fCPU). User's Manual U15836EJ4V0UD 409 CHAPTER 28 CAUTIONS FOR WAIT 28.3 Example of Wait Occurrence <1> Watchdog timer Value of Bit 5 (FR2) of ADM Register 0 fX fX/2 fX/2 fX/2 fX/2 1 fX fX/2 fX/2 fX/2 fX/2 2 2 fCPU Number of Wait Clocks 9 clocks 5 clocks 3 clocks 2 clocks 0 clocks (1 clock 5 clocks 3 clocks 2 clocks 0 clocks (1 clock 0 clocks (1 clock Note Note Number of Execution Clocks 14 clocks 10 clocks 8 clocks 7 clocks 3 4 ) 5 clocks (6 clocks 10 clocks 8 clocks 7 clocks Note ) 3 ) ) 5 clocks (6 clocks 5 clocks (6 clocks Note ) ) 4 Note Note Note On execution of MOV A, ADCR Remark The clock is the CPU clock (fCPU). fX: X1 input clock frequency tCPUL: Low-level width of CPU clock 410 User's Manual U15836EJ4V0UD APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the 78K0/KB1. Figure A-1 shows the development tool configuration. * Support for PC98-NX series Unless otherwise specified, products supported by IBM PC/ATTM compatibles are compatible with PC98-NX series computers. When using PC98-NX series computers, refer to the explanation for IBM PC/AT compatibles. * Windows Unless otherwise specified, "Windows" means the following OSs. * Windows 3.1 * Windows 95, 98, 2000 * Windows NTTM Ver 4.0 User's Manual U15836EJ4V0UD 411 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration (1/2) (1) When using the in-circuit emulators IE-78K0-NS, IE-78K0-NS-A Software package * Software package Language processing software * Assembler package * C compiler package * Device file * C library source fileNote 1 Debugging software * Integrated debugger * System simulator Control software * Project manager (Windows only)Note 2 Embedded software * Real-time OS Host machine (PC or EWS) Interface adapter, PC card interface, etc. Power supply unit Flash memory write environment Flash programmer In-circuit emulatorNote 3 Emulation board Flash memory write adapter Performance board Flash memory Emulation probe Conversion socket or conversion adapter Target system Notes 1. 2. 3. The C library source file is not included in the software package. The project manager is included in the assembler package. The project manager is only used for Windows. Products other than in-circuit emulators IE-78K0-NS and IE-78K0-NS-A are all sold separately. 412 User's Manual U15836EJ4V0UD APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration (2/2) (2) When using the in-circuit emulator IE-78K0K1-ET Software package * Software package Language processing software * Assembler package * C compiler package * Device file * C library source fileNote 1 Debugging software * Integrated debugger * System simulator Control software * Project manager (Windows only)Note 2 Embedded software * Real-time OS Host machine (PC or EWS) Interface adapter, PC card interface, etc. Flash memory write environment Flash programmer Power supply unit In-circuit emulatorNote 3 Flash memory write adapter Emulation probe Flash memory Conversion socket or conversion adapter Target system Notes 1. 2. 3. The C library source file is not included in the software package. The project manager is included in the assembler package. The project manager is only used for Windows. In-circuit emulator IE-78K0K1-ET is supplied with integrated debugger ID78K0-NS, a device file, power supply unit, and PCI bus interface adapter IE-70000-PCI-IF-A. Any other products are sold separately. User's Manual U15836EJ4V0UD 413 APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP78K0 78K/0 Series software package Development tools (software) common to the 78K/0 Series are combined in this package. Part number: SxxxxSP78K0 Remark xxxx in the part number differs depending on the host machine and OS used. SxxxxSP78K0 xxxx AB17 BB17 Host Machine PC-9800 series, IBM PC/AT compatibles OS Windows (Japanese version) Windows (English version) Supply Medium CD-ROM 414 User's Manual U15836EJ4V0UD APPENDIX A DEVELOPMENT TOOLS A.2 Language Processing Software RA78K0 Assembler package This assembler converts programs written in mnemonics into object codes executable with a microcontroller. This assembler is also provided with functions capable of automatically creating symbol tables and branch instruction optimization. This assembler should be used in combination with a device file (DF780103) (sold separately). Note 1 This file contains information peculiar to the device. This device file should be used in combination with a tool (RA78K0, CC78K0, SM78K0, ID78K0-NS, and ID78K0) (all sold separately). The corresponding OS and host machine differ depending on the tool to be used. Part number: SxxxxDF780103 CC78K0-L Note 2 This is a source file of the functions that configure the object library included in the C compiler package. This file is required to match the object library included in the C compiler package to the user's specifications. Since this is a source file, its working environment does not depend on any particular operating system. Part number: SxxxxCC78K0-L C library source file Notes 1. 2. The DF780103 can be used in common with the RA78K0, CC78K0, SM78K0, ID78K0-NS, and ID78K0. The CC78K0-L is not included in the software package (SP78K0). User's Manual U15836EJ4V0UD 415 APPENDIX A DEVELOPMENT TOOLS Remark xxxx in the part number differs depending on the host machine and OS used. SxxxxRA78K0 SxxxxCC78K0 xxxx AB13 BB13 AB17 BB17 3P17 3K17 HP9000 series 700 SPARCstation TM TM Host Machine PC-9800 series, IBM PC/AT compatibles OS Windows (Japanese version) Windows (English version) Windows (Japanese version) Windows (English version) HP-UX TM Supply Medium 3.5-inch 2HD FD CD-ROM (Rel. 10.10) (Rel. 4.1.4), (Rel. 2.5.1) SunOS Solaris TM TM SxxxxDF780103 SxxxxCC78K0-L xxxx AB13 BB13 3P16 3K13 3K15 Host Machine PC-9800 series, IBM PC/AT compatibles HP9000 series 700 SPARCstation OS Windows (Japanese version) Windows (English version) HP-UX (Rel. 10.10) SunOS (Rel. 4.1.4), Solaris (Rel. 2.5.1) DAT 3.5-inch 2HD FD 1/4-inch CGMT Supply Medium 3.5-inch 2HD FD A.3 Control Software Project manager This is control software designed to enable efficient user program development in the Windows environment. All operations used in development of a user program, such as starting the editor, building, and starting the debugger, can be performed from the project manager. A.4 Flash Memory Writing Tools Flashpro III (part number: FL-PR3, PG-FP3) Flashpro IV (part number: FL-PR4, PG-FP4) Flash programmer FA-30MC Flash memory writing adapter Flash memory writing adapter used connected to the Flashpro III/Flashpro IV. * FA-30MC: For 30-pin plastic SSOP (MC-5A4 type) Flash programmer dedicated to microcontrollers with on-chip flash memory. Remark FL-PR3, FL-PR4, and FA-30MC are products of Naito Densei Machida Mfg. Co., Ltd. TEL: +81-45-475-4191 Naito Densei Machida Mfg. Co., Ltd. 416 User's Manual U15836EJ4V0UD APPENDIX A DEVELOPMENT TOOLS A.5 Debugging Tools (Hardware) A.5.1 When using in-circuit emulators IE-78K0-NS and IE-78K0-NS-A IE-78K0-NS In-circuit emulator The in-circuit emulator serves to debug hardware and software when developing application systems using a 78K/0 Series product. It corresponds to the integrated debugger (ID78K0-NS). This emulator should be used in combination with a power supply unit, emulation probe, and the interface adapter required to connect this emulator to the host machine. IE-78K0-NS-PA Performance board This board is connected to the IE-78K0-NS to expand its functions. Adding this board adds a coverage function and enhances debugging functions such as tracer and timer functions. IE-78K0-NS-A In-circuit emulator IE-70000-MC-PS-B Power supply unit IE-70000-98-IF-C Interface adapter IE-70000-CD-IF-A PC card interface IE-70000-PC-IF-C Interface adapter IE-70000-PCI-IF-A Interface adapter IE-780148-NS-EM1 Emulation board NP-30MC Emulation probe NSPACK30BK YSPACK30BK HSPACK30BK YQ-Guide Conversion socket This board emulates the operations of the peripheral hardware peculiar to a device. It should be used in combination with an in-circuit emulator. This probe is used to connect the in-circuit emulator to the target system and is designed for use with a 30-pin plastic SSOP (MC-5A4 type). This conversion socket connects the NP-30MC to a target system board designed to mount a 30-pin plastic SSOP (MC-5A4 type). * NSPACK30BK: Socket for connecting target * YSPACK30BK: Socket for connecting emulator * HSPACK30BK: Cover for mounting device * YQ-Guide: Guide pin This adapter is required when using a PC-9800 series computer (except notebook type) as the host machine (C bus compatible). This is PC card and interface cable required when using a notebook-type computer as the host machine (PCMCIA socket compatible). This adapter is required when using an IBM PC compatible computer as the host machine (ISA bus compatible). This adapter is required when using a computer with a PCI bus as the host machine. This adapter is used for supplying power from a 100 V to 240 V AC outlet. Product that combines the IE-78K0-NS and IE-78K0-NS-PA Remarks 1. NP-30MC is a product of Naito Densei Machida Mfg. Co., Ltd. TEL: +81-45-475-4191 Naito Densei Machida Mfg. Co., Ltd. 2. NSPACK30BK, YSPACK30BK, HSPACK30BK, and YQ-Guide are products of TOKYO ELETECH CORPORATION. For further information, contact Daimaru Kogyo Co., Ltd. Tokyo Electronics Department (TEL: +81-3-3820-7112) Osaka Electronics Department (TEL: +81-6-6244-6672) User's Manual U15836EJ4V0UD 417 APPENDIX A DEVELOPMENT TOOLS A.5.2 When using in-circuit emulator IE-78K0K1-ET IE-78K0K1-ET Note The in-circuit emulator serves to debug hardware and software when developing application systems using a 78K0/Kx1 product. It corresponds to the integrated debugger (ID78K0-NS). This emulator should be used in combination with a power supply unit, emulation probe, and the interface adapter required to connect this emulator to the host machine. In-circuit emulator IE-70000-98-IF-C Interface adapter IE-70000-CD-IF-A PC card interface IE-70000-PC-IF-C Interface adapter IE-70000-PCI-IF-A Interface adapter NP-30MC Emulation probe NSPACK30BK YSPACK30BK HSPACK30BK YQ-Guide Conversion socket This adapter is required when using a PC-9800 series computer (except notebook type) as the host machine (C bus compatible). This is PC card and interface cable required when using a notebook-type computer as the host machine (PCMCIA socket compatible). This adapter is required when using an IBM PC compatible computer as the host machine (ISA bus compatible). This adapter is required when using a computer with a PCI bus as the host machine. This is supplied with IE-78K0K1-ET. This probe is used to connect the in-circuit emulator to the target system and is designed for use with a 30-pin plastic SSOP (MC-5A4 type). This conversion socket connects the NP-30MC to a target system board designed to mount a 30-pin plastic SSOP (MC-5A4 type). * NSPACK30BK: Socket for connecting target * YSPACK30BK: Socket for connecting emulator * HSPACK30BK: Cover for mounting device * YQ-Guide: Guide pin Note IE-78K0K1-ET is supplied with a power supply unit and PCI bus interface adapter IE-70000-PCI-IF-A. It is also supplied with integrated debugger ID78K0-NS and a device file as control software. Remarks 1. NP-30MC is a product of Naito Densei Machida Mfg. Co., Ltd. TEL: +81-45-475-4191 Naito Densei Machida Mfg. Co., Ltd. 2. NSPACK30BK, YSPACK30BK, HSPACK30BK, and YQ-Guide are products of TOKYO ELETECH CORPORATION. For further information, contact Daimaru Kogyo Co., Ltd. Tokyo Electronics Department (TEL: +81-3-3820-7112) Osaka Electronics Department (TEL: +81-6-6244-6672) 418 User's Manual U15836EJ4V0UD APPENDIX A DEVELOPMENT TOOLS A.6 Debugging Tools (Software) SM78K0 System simulator This is a system simulator for the 78K/0 Series. The SM78K0 is Windows-based software. It is used to perform debugging at the C source level or assembler level while simulating the operation of the target system on a host machine. Use of the SM78K0 allows the execution of application logical testing and performance testing on an independent basis from hardware development, thereby providing higher development efficiency and software quality. The SM78K0 should be used in combination with the device file (DF780103) (sold separately). Part number: SxxxxSM78K0 ID78K0-NS Integrated debugger (supporting in-circuit emulator IE-78K0-NS, IE-78K0-NS-A, IE-78K0K1-ET) This debugger supports the in-circuit emulators for the 78K/0 Series. The ID78K0-NS is Windows-based software. It has improved C-compatible debugging functions and can be display the results of tracing with the source program using an integrating window function that associates the source program, disassemble display, and memory display with the trace result. It should be used in combination with the device file (sold separately). Part number: SxxxxID78K0-NS Remark xxxx in the part number differs depending on the host machine and OS used. SxxxxSM78K0 SxxxxID78K0-NS xxxx AB13 BB13 AB17 BB17 Host Machine PC-9800 series, IBM PC/AT compatibles OS Windows (Japanese version) Windows (English version) Windows (Japanese version) Windows (English version) CD-ROM Supply Medium 3.5-inch 2HD FD User's Manual U15836EJ4V0UD 419 APPENDIX A DEVELOPMENT TOOLS A.7 Embedded Software RX78K0 Real-time OS The RX78K0 is a real-time OS conforming to the ITRON specifications. A tool (configurator) for generating the nucleus of the RX78K0 and multiple information tables is supplied. Used in combination with an assembler package (RA78K0) and device file (DF780103) (both sold separately). Caution To purchase the RX78K0, first fill in the purchase application form and sign the user agreement. Remark xxxx and in the part number differ depending on the host machine and OS used. SxxxxRX78013- 001 100K 001M 010M S01 Source program Product Outline Evaluation object Mass-production object Maximum Number for Use in Mass Production Do not use for mass-produced product. 0.1 million units 1 million units 10 million units Object source program for mass production xxxx AA13 AB13 BB13 Host Machine PC-9800 series IBM PC/AT compatibles OS Windows (Japanese version) Windows (Japanese version) Windows (English version) Supply Medium 3.5-inch 2HD FD 420 User's Manual U15836EJ4V0UD APPENDIX B NOTES ON TARGET SYSTEM DESIGN The following show the conditions when connecting the emulation probe to the conversion adapter. Follow the configuration below and consider the shape of parts to be mounted on the target system when designing a system. Figure B-1. Distance Between In-Circuit Emulator and Conversion Adapter In-circuit emulator IE-78K0S-NS, IE-78K0S-NS-A, or IE-78K0K1-ET Target system Emulation board IE-780148-NS-EM1 Board on end of NP-30MC 150 mm CN1 Emulation probe NP-30MC Conversion adapter: YSPACK30BK, NSPACK30BK 78010X PROBE Board Remarks 1. The NP-30MC product of Naito Densei Machida Mfg. Co., Ltd. 2. The YSPACK30BK and NSPACK30BK are products of TOKYO ELETECH CORPORATION. User's Manual U15836EJ4V0UD 421 APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figure B-2. Connection Condition of Target System Emulation board IE-780148-NS-EM1 Emulation probe NP-30MC Board on end of NP-30MC Guide pin YQ-Guide 13 mm Conversion adapter YSPACK30BK, NSPACK30BK 5 mm 15 mm 37 mm 20 mm 31 mm Target system Remarks 1. NP-30MC is a product of Naito Densei Machida Mfg. Co., Ltd. 2. YSPACK30BK, NSPACK30BK, and YQ-Guide are products of TOKYO ELETECH CORPORATION. 422 User's Manual U15836EJ4V0UD APPENDIX C REGISTER INDEX C.1 Register Index (In Alphabetical Order with Respect to Register Names) [A] A/D conversion result register (ADCR) ... 187 A/D converter mode register (ADM) ... 185 Analog input channel specification register (ADS) ... 187 Asynchronous serial interface control register 6 (ASICL6) ... 236 Asynchronous serial interface operation mode register 0 (ASIM0) ... 206 Asynchronous serial interface operation mode register 6 (ASIM6) ... 230 Asynchronous serial interface reception error status register 0 (ASIS0) ... 208 Asynchronous serial interface reception error status register 6 (ASIS6) ... 232 Asynchronous serial interface transmission status register 6 (ASIF6) ... 233 [B] Baud rate generator control register 0 (BRGC0) ... 209 Baud rate generator control register 6 (BRGC6) ... 235 [C] Capture/compare control register 00 (CRC00) ... 111 Clock monitor mode register (CLM) ... 310 Clock selection register 6 (CKSR6) ... 234 [E] 8-bit timer compare register 50 (CR50) ... 144 8-bit timer counter 50 (TM50) ... 143 8-bit timer H compare register 00 (CMP00) ... 158 8-bit timer H compare register 01 (CMP01) ... 158 8-bit timer H compare register 10 (CMP10) ... 158 8-bit timer H compare register 11 (CMP11) ... 158 8-bit timer H mode register 0 (TMHMD0) ... 159 8-bit timer H mode register 1 (TMHMD1) ... 159 8-bit timer mode control register 50 (TMC50) ... 146 External interrupt falling edge enable register (EGN) ... 282 External interrupt rising edge enable register (EGP) ... 282 [I] Input switch control register (ISC) ... 237 Internal memory size switching register (IMS) ... 332 Interrupt mask flag register 0H (MK0H) ... 280 Interrupt mask flag register 0L (MK0L) ... 280 Interrupt mask flag register 1L (MK1L) ... 280 Interrupt request flag register 0H (IF0H) ... 279 Interrupt request flag register 0L (IF0L) ... 279 Interrupt request flag register 1L (IF1L) ... 279 User's Manual U15836EJ4V0UD 423 APPENDIX C REGISTER INDEX [L] Low-voltage detection level selection register (LVIS) ... 322 Low-voltage detection register (LVIM) ... 321 [M] Main clock mode register (MCM) ... 89 Main OSC control register (MOC) ... 90 [O] Oscillation stabilization time counter status register (OSTC) ... 91, 293 Oscillation stabilization time select register (OSTS) ... 92, 294 [P] Port mode register 0 (PM0) ... 80, 114 Port mode register 1 (PM1) ... 80, 147, 162, 210, 237, 265 Port mode register 12 (PM12) ... 80 Port mode register 3 (PM3) ... 80 Port register 0 (P0) ... 82 Port register 1 (P1) ... 82 Port register 12 (P12) ... 82 Port register 13 (P13) ... 82 Port register 2 (P2) ... 82 Port register 3 (P3) ... 82 Power-fail comparison mode register (PFM) ... 188 Power-fail comparison threshold register (PFT) ... 188 Prescaler mode register 00 (PRM00) ... 113 Priority specification flag register 0H (PR0H) ... 281 Priority specification flag register 0L (PR0L) ... 281 Priority specification flag register 1L (PR1L) ... 281 Processor clock control register (PCC) ... 87 Pull-up resistor option register 0 (PU0) ... 83 Pull-up resistor option register 1 (PU1) ... 83 Pull-up resistor option register 12 (PU12) ... 83 Pull-up resistor option register 3 (PU3) ... 83 [R] Receive buffer register 0 (RXB0) ... 205 Receive buffer register 6 (RXB6) ... 229 Reset control flag register (RESF) ... 308 Ring-OSC mode register (RCM) ... 88 [S] Serial clock selection register 10 (CSIC10) ... 264 Serial operation mode register 10 (CSIM10) ... 263 Serial I/O shift register 10 (SIO10) ... 262 16-bit timer capture/compare register 000 (CR000) ... 106 16-bit timer capture/compare register 010 (CR010) ... 108 16-bit timer counter 00 (TM00) ... 106 424 User's Manual U15836EJ4V0UD APPENDIX C REGISTER INDEX 16-bit timer mode control register 00 (TMC00) ... 109 16-bit timer output control register 00 (TOC00) ... 111 [T] Timer clock selection register 50 (TCL50) ... 145 Transmit buffer register 10 (SOTB10) ... 262 Transmit buffer register 6 (TXB6) ... 229 Transmit shift register 0 (TXS0) ... 205 [W] Watchdog timer enable register (WDTE) ... 176 Watchdog timer mode register (WDTM) ... 175 User's Manual U15836EJ4V0UD 425 APPENDIX C REGISTER INDEX C.2 Register Index (In Alphabetical Order with Respect to Register Symbol) [A] ADCR: ADM: ADS: ASICL6: ASIF6: ASIM0: ASIM6: ASIS0: ASIS6: [B] BRGC0: BRGC6: [C] CKSR6: CLM: CMP00: CMP01: CMP10: CMP11: CR000: CR010: CR50: CRC00: CSIC10: CSIM10: [E] EGN: EGP: [I] IF0H: IF0L: IF1L: IMS: ISC: [L] LVIM: LVIS: [M] MCM: Main clock mode register ... 89 User's Manual U15836EJ4V0UD A/D conversion result register ... 187 A/D converter mode register ... 185 Analog input channel specification register ... 187 Asynchronous serial interface control register 6 ... 236 Asynchronous serial interface transmission status register 6 ... 233 Asynchronous serial interface operation mode register 0 ... 206 Asynchronous serial interface operation mode register 6 ... 230 Asynchronous serial interface reception error status register 0 ... 208 Asynchronous serial interface reception error status register 6 ... 232 Baud rate generator control register 0 ... 209 Baud rate generator control register 6 ... 235 Clock selection register 6 ... 234 Clock monitor mode register ... 310 8-bit timer H compare register 00 ... 158 8-bit timer H compare register 01 ... 158 8-bit timer H compare register 10 ... 158 8-bit timer H compare register 11 ... 158 16-bit timer capture/compare register 000 ... 106 16-bit timer capture/compare register 010 ... 108 8-bit timer compare register 50 ... 144 Capture/compare control register 00 ... 111 Serial clock selection register 10 ... 264 Serial operation mode register 10 ... 263 External interrupt falling edge enable register ... 282 External interrupt rising edge enable register ... 282 Interrupt request flag register 0H ... 279 Interrupt request flag register 0L ... 279 Interrupt request flag register 1L ... 279 Internal memory size switching register ... 332 Input switch control register ... 237 Low-voltage detection register ... 321 Low-voltage detection level selection register ... 322 426 APPENDIX C REGISTER INDEX MK0H: MK0L: MK1L: MOC: [O] OSTC: OSTS: [P] P0: P1: P12: P13: P2: P3: PCC: PFM: PFT: PM0: PM1: PM12: PM3: PR0H: PR0L: PR1L: PRM00: PU0: PU1: PU12: PU3: [R] RCM: RESF: RXB0: RXB6: [S] SIO10: SOTB10: [T] TCL50: TM00: TM50: TMC00: TMC50: Interrupt mask flag register 0H ... 280 Interrupt mask flag register 0L ... 280 Interrupt mask flag register 1L ... 280 Main OSC control register ... 90 Oscillation stabilization time counter status register ... 91, 293 Oscillation stabilization time select register ... 92, 294 Port register 0 ... 82 Port register 1 ... 82 Port register 12 ... 82 Port register 13 ... 82 Port register 2 ... 82 Port register 3 ... 82 Processor clock control register ... 87 Power-fail comparison mode register ... 188 Power-fail comparison threshold register ... 188 Port mode register 0 ... 80, 114 Port mode register 1 ... 80, 147, 162, 210, 237, 265 Port mode register 12 ... 80 Port mode register 3 ... 80 Priority specification flag register 0H ... 281 Priority specification flag register 0L ... 281 Priority specification flag register 1L ... 281 Prescaler mode register 00 ... 113 Pull-up resistor option register 0 ... 83 Pull-up resistor option register 1 ... 83 Pull-up resistor option register 12 ... 83 Pull-up resistor option register 3 ... 83 Ring-OSC mode register ... 88 Reset control flag register ... 308 Receive buffer register 0 ... 205 Receive buffer register 6 ... 229 Serial I/O shift register 10 ... 262 Transmit buffer register 10 ... 262 Timer clock selection register 50 ... 145 16-bit timer counter 00 ... 106 8-bit timer counter 50 ... 143 16-bit timer mode control register 00 ... 109 8-bit timer mode control register 50 ... 146 User's Manual U15836EJ4V0UD 427 APPENDIX C REGISTER INDEX TMHMD0: TMHMD1: TOC00: TXB6: TXS0: [W] WDTE: WDTM: 8-bit timer H mode register 0 ... 159 8-bit timer H mode register 1 ... 159 16-bit timer output control register 00 ... 111 Transmit buffer register 6 ... 229 Transmit shift register 0 ... 205 Watchdog timer enable register ... 176 Watchdog timer mode register ... 175 428 User's Manual U15836EJ4V0UD APPENDIX D REVISION HISTORY D.1 Major Revisions in This Edition (1/4) Page Throughout Addition of products Description PD780101(A2), 780102(A2), 780103(A2) Modification of names of the following special function registers (SFRs) * Ports 0 to 3, 12, and 13 Port registers 0 to 3, 12, and 13 p. 20 p. 21 p. 27 p. 28 p. 67 p. 68 p. 80 Addition of Cautions 3 to 1.4 Pin Configuration (Top View) Modification of 1.5 K1 Family Lineup Modification of outline of timer in 1.7 Outline of Functions Addition of Table 2-1 Pin I/O Buffer Power Supplies Addition of Table 4-1 Pin I/O Buffer Power Supplies Modification of Table 4-3 Port Configuration Deletion of input switch control register (ISC) from and addition of port registers (P0 to P3, P12, and P13) to 4.3 Registers Controlling Port Function p. 86 p. 91 Modification of Figure 5-1 Block Diagram of Clock Generator Addition of Cautions 2 and 3 to Figure 5-6 Format of Oscillation Stabilization Time Counter Status Register (OSTC) pp. 93, 94 Modification of Figure 5-8 External Circuit of X1 Oscillator and Figure 5-9 Examples of Incorrect Resonator Connection p. 101 Modification of Note in Figure 5-12 Switching from Ring-OSC Clock to X1 Input Clock (Flowchart) Addition of figures p. 106 p. 106 p. 108 * Figure 6-2 Format of 16-Bit Timer Counter 00 (TM00) * Figure 6-3 Format of 16-Bit Timer Capture/Compare Register 000 (CR000) * Figure 6-4 Format of 16-Bit Timer Capture/Compare Register 010 (CR010) Modification of tables p. 107 p. 108 p. 108 p. 111 * Table 6-2 CR000 Capture Trigger and Valid Edges of TI000 and TI010 Pins * Table 6-3 CR010 Capture Trigger and Valid Edge of TI000 Pin (CRC002 = 1) Modification of Caution 1 in 6.2 (3) 16-Bit Timer Capture/Compare Register 010 (CR010) Modification of Caution 3 to Figure 6-6 Format of Capture/Compare Control Register 00 (CRC00) p. 112 Addition of description to Caution 5 in Figure 6-7 Format of 16-Bit Timer Output Control Register 00 (TOC00), addition of Caution 6 Addition of register settings p. 115 p. 118 p. 121 p. 129 p. 132 p. 134 * 6.4.1 Interval timer operation * 6.4.2 PPG output operations * 6.4.3 Pulse width measurement operations * 6.4.4 External event counter operation * 6.4.5 Square-wave output operation * 6.4.6 One-shot pulse output operation User's Manual U15836EJ4V0UD 429 APPENDIX D REVISION HISTORY (2/4) Page Description Addition of setting to prescaler mode register 00 (PRM00) p. 116 p. 119 p. 122 p. 124 p. 126 p. 128 p. 130 p. 133 p. 135 p. 137 * Figure 6-10 Control Register Settings for Interval Timer Operation * Figure 6-13 Control Register Settings for PPG Output Operation * Figure 6-17 Control Register Settings for Pulse Width Measurement with Free-Running Counter and One Capture Register (When TI000 and CR010 Are Used) * Figure 6-20 Control Register Settings for Measurement of Two Pulse Widths with FreeRunning Counter * Figure 6-22 Control Register Settings for Pulse Width Measurement with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) * Figure 6-24 Control Register Settings for Pulse Width Measurement by Means of Restart (with Rising Edge Specified) * Figure 6-26 Control Register Settings in External Event Counter Mode (with Rising Edge Specified) * Figure 6-29 Control Register Settings in Square-Wave Output Mode * Figure 6-31 Control Register Settings for One-Shot Pulse Output with Software Trigger * Figure 6-33 Control Register Settings for One-Shot Pulse Output with External Trigger (with Rising Edge Specified) Modification of figures p. 117 p. 120 p. 138 * Figure 6-12 Timing of Interval Timer Operation * Figure 6-15 PPG Output Operation Timing * Figure 6-34 Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified) Addition of figures p. 143 p. 144 p. 148 p. 151 p. 152 * Figure 7-2 Format of 8-Bit Timer Counter 50 (TM50) * Figure 7-3 Format of 8-Bit Timer Compare Register 50 (CR50) Modification of Figure 7-7 Interval Timer Operation Timing Modification of description of frequency in 7.4.3 Operation as square-wave output Addition of description of cycle, active level width, and duty to 7.4.4 (1) PWM output basic operation p. 168 p. 182 p. 183 p. 185 Modification of Figure 8-11 Operation Timing in PWM Output Mode Modification of Figure 10-1 Block Diagram of A/D Converter Partial modification of description of 10.2 Configuration of A/D Converter Addition of description of A/D conversion result register (ADCR) to 10.3 Registers Used in A/D Converter p. 189 p. 191 Partial modification of description of 10.4.1 Basic operations of A/D converter Addition of description of successive approximation register (SAR) to 10.4.2 Input voltage and conversion results p. 194 Modification of Caution 3 in "When used as power-fail function" in 10.4.3 A/D converter operation mode p. 200 Modification of Figure 10-21 Timing of A/D Converter Sampling and A/D Conversion Start Delay 430 User's Manual U15836EJ4V0UD APPENDIX D REVISION HISTORY (3/4) Page p. 201 pp. 206, 207 Description Addition of description of (12) Internal equivalent circuit to 10.6 Cautions for A/D Converter Modification of Cautions 1, 2, 4 and addition of Note 2 and Caution 3 to Figure 11-2 Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) p. 211 p. 212 Modification of description of 11.4.1 Operation stop mode Modification of description of 11.4.2 Asynchronous serial interface (UART) mode (1) Registers used p. 217 Modification of Table 11-3 Cause of Reception Error Modification of figures p. 224 p. 225 p. 226 p. 228 pp. 230, 231 * Figure 12-1 LIN Transmission Operation * Figure 12-2 LIN Reception Operation * Figure 12-3 Port Configuration for LIN Reception Operation * Figure 12-4 Block Diagram of Serial Interface UART6 Modification of Cautions 1, 2 and addition of Note 2 and Caution 3 to Figure 12-5 Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) p. 230 Addition of input switch control register (ISC) to 12.3 Registers Controlling Serial Interface UART6 p. 238 p. 239 Modification of description of 12.4.1 Operation stop mode Modification of description of 12.4.2 Asynchronous Serial Interface (UART) mode (1) Registers used p. 245 p. 250 p. 262 p. 263 Modification of description of 12.4.2 (2) (d) Continuous transmission Modification of Table 12-3 Cause of Reception Error Modification of Figure 13-1 Block Diagram of Serial Interface CSI10 Addition of Notes 2 and 3 to Figure 13-2 Format of Serial Operation Mode Register 10 (CSIM10) p. 264 Modification of Caution 2 and addition of Caution 3 to Figure 13-3 Format of Serial Clock Selection Register 10 (CSIC10) p. 266 p. 267 p. 274 p. 279 Modification of description of 13.4.1 Operation stop mode Modification of description of 13.4.2 3-wire serial I/O mode (1) Registers used Addition of (5) SO10 output to 13.4.2 3-wire serial I/O mode Addition of Caution 3 to Figure 14-2 Format of Interrupt Request Flag Register (IF0L, IF0H, IF1L) p. 291 Modification of Table 15-1 Relationship Between HALT and STOP Modes and Clock in old edition to Table 15-1 Relationship Between Operation Clocks in Each Operation Status p. 293 Addition of Cautions 2 and 3 to Figure 15-1 Format of Oscillation Stabilization Time Counter Status Register (OSTC) p. 295 Modification of Table 15-2 Operating Statuses in HALT Mode Modification of figures p. 303 p. 304 p. 304 p. 305 p. 309 p. 311 * Figure 16-1 Block Diagram of Reset Function * Figure 16-2 Timing of Reset by RESET Input * Figure 16-3 Timing of Reset Due to Watchdog Timer Overflow * Figure 16-4 Timing of Reset in STOP Mode by RESET Input Modification of Figure 17-1 Block Diagram of Clock Monitor Addition of normal operation mode to Table 17-2 Operation Status of Clock Monitor (When CLME = 1) User's Manual U15836EJ4V0UD 431 APPENDIX D REVISION HISTORY (4/4) Page pp. 314, 315 Description Addition of (6) Clock monitor status after X1 input clock oscillation is stopped by software and (7) Clock monitor status after Ring-OSC clock oscillation is stopped by software to Figure 17-3 Timing of Clock Monitor p. 317 p. 320 p. 322 Modification of Figure 18-1 Block Diagram of Power-on-Clear Circuit Modification of Figure 19-1 Block Diagram of Low-Voltage Detector Addition of Caution to Figure 19-3 Format of Low-Voltage Detection Level Selection Register (LVIS) pp. 324, 326 Modification of Figure 19-4 Timing of Low-Voltage Detector Internal Reset Signal Generation and Figure 19-5 Timing of Low-Voltage Detector Interrupt Signal Generation p. 329 Partial modification of description of (2) When used as interrupt under 432 User's Manual U15836EJ4V0UD APPENDIX D REVISION HISTORY D.2 Revision History of Previous Editions A history of the revisions up to this edition is shown below. "Applied to:" indicates the chapters to which the revision was applied. (1/5) Edition 2nd 12 14 15 16 17 11 Description X1 input clock oscillation stabilization time 2 /fX, 2 /fX, 2 /fX, 2 /fX, 2 /fX 2 /fX, 2 /fX, 2 /fX, 2 /fX, 2 /fX 13 14 15 16 Applied to: Throughout Modification of Figure 4-5 Block Diagram of P10 Modification of Table 4-3 Settings of Port Mode Register and Output Latch When Alternate-Function Is Used Modification of Figure 5-6 Format of Oscillation Stabilization Time Counter Status Register (OSTC) Modification of Figure 5-7 Format of Oscillation Stabilization Time Select Register (OSTS) Addition of 5.7 Clock Selection Flowchart and Register Settings Addition of Remark to 12.1 Functions of Serial Interface UART6 CHAPTER 4 PORT FUNCTIONS CHAPTER 5 CLOCK GENERATOR CHAPTER 12 SERIAL INTERFACE UART6 Addition of Reset to Table 14-1 Interrupt Source List CHAPTER 14 INTERRUPT FUNCTIONS Modification of Figure 15-2 Format of Oscillation Stabilization Time Counter Status Register (OSTC) Modification of Figure 15-3 Format of Oscillation Stabilization Time Select Register (OSTS) Addition of CHAPTER 25 RETRY 2nd edition) Modification of reset value of the following register in Table 3-5 Special Function * Serial I/O shift register 10 (SIO10) Modification of manipulatable bit unit of the following registers in Table 3-5 Special Function Register List * Oscillation stabilization time counter status register (OSTC) * Interrupt request flag register 1L (IF1L) * Interrupt mask flag register 1L (MK1L) * Priority specification flag register 1L (PR1L) Modification of manipulatable bit unit in 5.3 (5) Oscillation stabilization time counter status register (OSTC) Modification of Figure 5-11 Status Transition Diagram Modification of Table 5-3 Relationship Between Operation Clocks in Each Operation Status Modification of Table 5-4 Oscillation Control Flags and Clock Oscillation Status Modification of Table 5-6 Clock and Register Settings Modification of reset value in 6.2 (2) 16-bit timer capture/compare register 000 (CR000) and (3) 16-bit timer capture/compare register 010 (CR010) Modification of manipulatable bit unit in 6.3 (4) Prescaler mode register 00 (PRM00) Modification of Caution in 9.4.2 Watchdog timer operation when "Ring-OSC can be stopped by software" is selected by mask option Modification of 9.4.3 Watchdog timer operation in STOP mode (when "Ring-OSC can be stopped by software" is selected by mask option) CHAPTER 15 STANDBY FUNCTION CHAPTER 25 RETRY CHAPTER 3 CPU ARCHITECTURE (corrected Register List CHAPTER 5 CLOCK GENERATOR CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 CHAPTER 9 WATCHDOG TIMER User's Manual U15836EJ4V0UD 433 APPENDIX D REVISION HISTORY (2/5) Edition 2nd edition) Description Addition of 9.4.4 Watchdog timer operation in HALT mode (when "Ring-OSC can Applied to: CHAPTER 9 WATCHDOG TIMER CHAPTER 10 A/D CONVERTER CHAPTER 13 SERIAL INTERFACE CSI10 Modification of manipulatable bit unit in 15.1.2 (1) Oscillation stabilization time counter status register (OSTC) Modification of A/D converter item in Table 15-2 Operating Statuses in HALT mode Addition of 18.4 Cautions for Power-on-Clear Circuit CHAPTER 18 POWER-ONCLEAR CIRCUIT Modification of Figure 19-3 Format of Low-Voltage Detection Level Selection Register (LVIS) Addition of 19.5 Cautions for Low-Voltage Detector Modification of the following contents in CHAPTER 23 ELECTRICAL SPECIFICATIONS (TARGET VALUES) * Absolute Maximum Ratings * X1 Oscillator Characteristics * DC Characteristics * A/D Converter Characteristics * POC Circuit Characteristics * LVI Circuit Characteristics * Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (deletion of data retention supply current) * Deletion of Ring-OSC Characteristics * Flash Memory Programming Characteristics Modification from CHAPTER 25 RETRY to CHAPTER 25 CAUTIONS FOR WAIT CHAPTER 25 CAUTIONS FOR WAIT 3rd Deletion of following products. * PD780101(A2), 780102(A2), 780103(A2) * PD78F0103M3MC(A1)-5A4, 78F0103M4MC(A1)-5A4 Modification of supply voltage range of (A1) product and ambient operating temperature of flash memory version of (A1) product Modification of reset value of A/D conversion result register (ADCR) (0000H undefined) Update of 1.6 78K0/K1 Series Lineup Modification of Figure 3-12 Data to Be Saved to Stack Memory Modification of Figure 3-13 Data to Be Restored from Stack Memory Modification of [Description example] in 3.4.4 Short direct addressing Addition of [Illustration] to 3.4.7 Based addressing, 3.4.8 Based indexed addressing, and 3.4.9 Stack addressing Modification of Figure 4-10 Block Diagram of P20 to P23 Addition of Remark to Figure 4-13 Block Diagram of P130 Addition of condition (set value of MCM0) to Figure 5-2 Format of Processor Clock Control Register (PCC) Partial modification of description in 5.5 Clock Generator Operation Addition of 5.7 Changing System Clock and CPU Clock Settings CHAPTER 4 PORT FUNCTIONS CHAPTER 5 CLOCK GENERATOR CHAPTER 1 OUTLINE CHAPTER 3 CPU ARCHITECTURE Throughout CHAPTER 23 ELECTRICAL SPECIFICATIONS (TARGET VALUES) CHAPTER 19 LOW-VOLTAGE DETECTOR CHAPTER 15 STANDBY FUNCTION (corrected be stopped by software" is selected by mask option) Addition of (11) A/D converter sampling time and A/D conversion start delay time in 10.6 Cautions for A/D Converter Modification of reset value in 13.2 (2) Serial I/O shift register 10 (SIO10) 434 User's Manual U15836EJ4V0UD APPENDIX D REVISION HISTORY (3/5) Edition 3rd Description Modification of Figure 6-1 Block Diagram of 16-Bit Timer/Event Counter 00 Modification of Cautions 1 and 2 in 6.2 (2) 16-bit timer capture/compare register 000 (CR000), and modification of Caution 1 in (3) 16-bit timer capture/compare register 010 (CR010) Addition of Caution 1 to Figure 6-5 Format of Prescaler Mode Register 00 (PRM00) Addition of Note to Figure 6-8 Interval Timer Configuration Diagram Modification of Caution 1 of Figure 6-10 Control Register Settings for PPG Output Operation Addition of Figure 6-11 Configuration of PPG Output and Figure 6-12 PPG Output Operation Timing Addition of Note to Figure 6-15 Timing of Pulse Width Measurement Operation with Free-Running Counter and One Capture Register (with Both Edges Specified), Figure 6-18 Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified), and Figure 6-20 Timing of Pulse Width Measurement Operation with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) Modification of Figure 6-24 Configuration Diagram of External Event Counter Addition of 6.4.6 One-shot pulse output operation Modification of Figure 6-34 Capture Register Data Retention Timing Addition of description <2> to 6.5 (4) Capture register data retention timing Deletion of 6.5 (7) Conflicting operations from old edition Modification of Figure 7-1 Block Diagram of 8-Bit Timer/Event Counter 50 Addition of Caution 1 to Figure 7-2 Format of Timer Clock Selection Register 50 (TCL50) Deletion of Caution 1 of old edition and modification of Caution 2 of Figure 7-3 Format of 8-Bit Timer Mode Control Register 50 (TMC50) Addition of Remark to Figure 7-8 PWM Output Operation Timing Addition of square-wave output to 8.1 Functions of 8-Bit Timers H0 and H1, and change of PWM pulse generator mode to PWM output Modification of Figure 8-1 Block Diagram of 8-Bit Timer H0 Modification of Figure 8-2 Block Diagram of 8-Bit Timer H1 Addition of Note and Caution 1 to Figure 8-3 Format of 8-Bit Timer H Mode Register 0 (TMHMD0) Addition of Figure 8-5 Format of Port Mode Register 1 (PM1) Change of 8.4.1 Operation as interval timer of old edition to 8.4.1 Operation as interval timer/square-wave output Modification of (a) Basic operation of Figure 8-7 Timing of Interval Timer/SquareWave Output Operation Modification of description of duty ratio in 8.4.2 (1) Usage Addition of description to 10.2 (2) A/D conversion result register (ADCR), modification of description in (3) Sample & hold circuit and (4) Voltage comparator, and partial modification of Caution 2 in (6) ANI0 to ANI3 pins Modification of Note 1 of Figure 10-4 Format of A/D Converter Mode Register (ADM) CHAPTER 10 A/D CONVERTER CHAPTER 8 8-BIT TIMERS H0 AND H1 CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50 Applied to: CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 User's Manual U15836EJ4V0UD 435 APPENDIX D REVISION HISTORY (4/5) Edition 3rd Description Modification of Figure 10-6 Format of Analog Input Channel Specification Register (ADS) Addition of description to 10.3 (3) Power-fail comparison mode register (PFM), and modification of Figure 10-7 Format of Power-Fail Comparison Mode Register (PFM) Modification of expressions in 10.4.2 Input voltage and conversion results Partial modification of description in 10.6 (5) ANI0/P20 to ANI3/P23 Addition of description to 10.6 (9) Conversion results just after A/D conversion start Modification of Caution 3 of 11.1 Functions of Serial Interface UART0 Modification of Figure 11-1 Block Diagram of Serial Interface UART0 Modification of Caution 3 in Figure 11-2 Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) and 11.4.2 (1) (a) Asynchronous serial interface operation mode register 0 (ASIM0) Addition of Note and Caution 1 to Figure 11-4 Format of Baud Rate Generator Control Register 0 (BRGC0) and 11.4.3 (2) (a) Baud rate generator control register 0 (BRGC0) Addition of Figure 11-5 Format of Port Mode Register 1 (PM1) and 11.4.2 (1) (c) Port mode register 1 (PM1) Modification of Figure 11-11 Configuration of Baud Rate Generator Modification of term in 11.4.3 (4) Permissible baud rate range during reception and 12.4.3 (4) Permissible baud rate range during reception as follows Transfer rate Data frame length Modification of Remark 1 in Table 11-4 Maximum/Minimum Permissible Baud Rate Error Addition of Figure 12-4 Format of Input Switch Control Register (ISC) Modification of Figure 12-5 Block Diagram of Serial Interface UART6 Addition of Note and Caution 1 to Figure 12-9 Format of Clock Selection Register 6 (CKSR6) and 12.4.3 (2) (a) Clock selection register 6 (CKSR6) Modification of Figure 12-11 Format of Asynchronous Serial Interface Control Register 6 (ASICL6) and 12.4.2 (1) (d) Asynchronous serial interface control register 6 (ASICL6) Addition of Figure 12-12 Format of Port Mode Register 1 (PM1) and 12.4.2 (1) (e) Port mode register 1 (PM1) Modification of description of 12.4.2 (2) (h) SBF transmission and addition of Figure 12-22 Example of Setting Procedure of SBF Transmission (Flowchart) Modification of Figure 12-25 Configuration of Baud Rate Generator Modification of Figure 13-1 Block Diagram of Serial Interface CSI10 Addition of Figure 13-4 Format of Port Mode Register 1 (PM1) and 13.4.2 (1) (c) Port mode register 1 (PM1) Modification of (C) Software interrupt in Figure 14-1 Basic Configuration of Interrupt Function Addition of Note 4 to Table 14-2 Flag Corresponding to Interrupt Request Sources Deletion of Caution 1 from Figure 14-3 Format of Interrupt Mask Flag Register (MK0L, MK0H, MK1L) of old edition Addition of Table 14-3 Ports Corresponding to EGPn and EGNn CHAPTER 14 INTERRUPT FUNCTIONS CHAPTER 13 SERIAL INTERFACE CSI10 CHAPTER 12 SERIAL INTERFACE UART6 CHAPTER 11 SERIAL INTERFACE UART0 (PD780102, 780103, 78F0103 ONLY) Applied to: CHAPTER 10 A/D CONVERTER 436 User's Manual U15836EJ4V0UD APPENDIX D REVISION HISTORY (5/5) Edition 3rd Description Addition of items of software interrupt requests to Table 14-5 Interrupt Request Enabled for Multiple Interrupt Servicing During Interrupt Servicing Modification of Table 15-1 Relationship Between HALT and STOP Modes and Clock Modification of following items in Table 15-2 Operating Statuses in HALT Mode and Table 15-4 Operating Statuses in STOP Mode * System clock * 16-bit timer/event counter 00 (Table 15-2 only) * 8-bit timer H0 * Watchdog timer * Serial interface UART0 * Serial interface UART6 Modification of Figure 16-1 Block Diagram of Reset Function CHAPTER 16 RESET FUNCTION Addition of description to (4) and (5) of Figure 17-3 Timing of Clock Monitor CHAPTER 17 CLOCK MONITOR Addition of Note to description of 18.1 Functions of Power-on-Clear Circuit Modification of Figure 18-1 Block Diagram of Power-on-Clear Circuit Addition of Note to description of 19.1 Functions of Low-Voltage Detector Modification of Figure 19-1 Block Diagram of Low-Voltage Detector Addition of Note 2 to Figure 19-3 Format of Low-Voltage Detection Level Selection Register (LVIS) Modification of Figure 19-7 Example of Software Processing of LVI Interrupt Addition of Note to description of CHAPTER 20 MASK OPTIONS Revision of CHAPTER 21 PD78F0103 (no change to 21.1 Internal Memory Size Switching Register) Revision of CHAPTER 23 ELECTRICAL SPECIFICATIONS CHAPTER 23 ELECTRICAL SPECIFICATIONS Addition of CHAPTER 25 RECOMMENDED SOLDERING CONDITIONS CHAPTER 25 RECOMMENDED SOLDERING CONDITIONS Addition of A.3 Control Software Deletion of `NP-36GS' and `NGS-30' from A.5 Debugging Tools (Hardware) of old edition, and addition of in-circuit emulator `IE-78K0K1-ET' Modification of ordering name of RX78K0 in A.7 Embedded Software Addition of APPENDIX B NOTES ON TARGET SYSTEM DESIGN APPENDIX B NOTES ON TARGET SYSTEM DESIGN APPENDIX A DEVELOPMENT TOOLS CHAPTER 20 MASK OPTIONS CHAPTER 21 PD78F0103 CHAPTER 18 POWER-ONCLEAR CIRCUIT CHAPTER 19 LOW-VOLTAGE DETECTOR Applied to: CHAPTER 14 INTERRUPT FUNCTIONS CHAPTER 15 STANDBY FUNCTION User's Manual U15836EJ4V0UD 437 |
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